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/**
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/*
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* @file
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* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
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* @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
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*
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* Licensed under the Apache License, Version 2.0 (the "License");
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* @brief Instruction Cache.
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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*/
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#ifndef __DEBUGGER_RIVERLIB_ICACHE_H__
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#ifndef __DEBUGGER_RIVERLIB_ICACHE_H__
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#define __DEBUGGER_RIVERLIB_ICACHE_H__
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#define __DEBUGGER_RIVERLIB_ICACHE_H__
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State_Idle,
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State_Idle,
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State_WaitGrant,
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State_WaitGrant,
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State_WaitResp,
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State_WaitResp,
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State_WaitAccept
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State_WaitAccept
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};
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};
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enum EHit {
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Hit_Line1,
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Hit_Line2,
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Hit_Response,
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Hit_Total
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};
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static const int ILINE_TOTAL = 2;
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struct line_type {
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sc_signal<sc_uint<BUS_ADDR_WIDTH - 3>> addr;
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sc_signal<sc_uint<BUS_DATA_WIDTH>> data;
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};
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struct line_signal_type {
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sc_bv<ILINE_TOTAL + 1> hit; // Hit_Total = ILINE_TOTAL + 1
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sc_bv<ILINE_TOTAL> hit_hold;
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sc_uint<BUS_DATA_WIDTH> hit_data;
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sc_uint<BUS_DATA_WIDTH> hold_data;
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};
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struct RegistersType {
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struct RegistersType {
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sc_signal<sc_uint<BUS_ADDR_WIDTH - 3>> iline_addr;
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line_type iline[ILINE_TOTAL];
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sc_signal<sc_uint<BUS_DATA_WIDTH>> iline_data;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> iline_addr_req;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> iline_addr_req;
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sc_signal<sc_uint<32>> iline_data_hit;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> addr_processing;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> iline_addr_hit;
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sc_signal<sc_uint<2>> state;
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sc_signal<sc_uint<2>> state;
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sc_signal<bool> hit_line;
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sc_signal<bool> double_req; // request 2-lines
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sc_signal<bool> delay_valid;
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sc_signal<sc_uint<32>> delay_data;
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} v, r;
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} v, r;
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bool w_hit_req;
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bool w_need_mem_req;
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bool w_hit_line;
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sc_uint<32> wb_hit_word;
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bool w_hit;
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line_signal_type wb_l[ILINE_TOTAL];
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bool w_reuse_lastline;
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bool w_wait_response;
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};
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};
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#ifdef DBG_ICACHE_TB
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#ifdef DBG_ICACHE_TB
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SC_MODULE(ICache_tb) {
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SC_MODULE(ICache_tb) {
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