URL
https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk
Show entire file |
Details |
Blame |
View Log
| Rev 3 |
Rev 4 |
| Line 1... |
Line 1... |
/**
|
/*
|
* @file
|
* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
|
* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
|
*
|
* @author Sergey Khabarov - sergeykhbr@gmail.com
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
* @brief Branch predictor.
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* http://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
*/
|
*/
|
|
|
#ifndef __DEBUGGER_RIVERLIB_BR_PREDIC_H__
|
#ifndef __DEBUGGER_RIVERLIB_BR_PREDIC_H__
|
#define __DEBUGGER_RIVERLIB_BR_PREDIC_H__
|
#define __DEBUGGER_RIVERLIB_BR_PREDIC_H__
|
|
|
| Line 35... |
Line 44... |
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
|
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
|
|
|
private:
|
private:
|
struct RegistersType {
|
struct RegistersType {
|
sc_signal<sc_uint<BUS_ADDR_WIDTH>> npc;
|
sc_signal<sc_uint<BUS_ADDR_WIDTH>> npc;
|
|
sc_signal<sc_uint<BUS_ADDR_WIDTH>> resp_mem_addr;
|
|
sc_signal<sc_uint<32>> resp_mem_data;
|
} v, r;
|
} v, r;
|
sc_signal<sc_uint<BUS_ADDR_WIDTH>> wb_npc;
|
sc_uint<BUS_ADDR_WIDTH> wb_npc;
|
};
|
};
|
|
|
|
|
} // namespace debugger
|
} // namespace debugger
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.