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/**
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/*
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* @file
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* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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*
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* Licensed under the Apache License, Version 2.0 (the "License");
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* @brief CPU Instruction Execution stage.
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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*/
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#ifndef __DEBUGGER_RIVERLIB_EXECUTE_H__
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#ifndef __DEBUGGER_RIVERLIB_EXECUTE_H__
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#define __DEBUGGER_RIVERLIB_EXECUTE_H__
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#define __DEBUGGER_RIVERLIB_EXECUTE_H__
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sc_in<bool> i_memop_load; // Load from memoru operation
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sc_in<bool> i_memop_load; // Load from memoru operation
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sc_in<bool> i_memop_sign_ext; // Load memory value with sign extending
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sc_in<bool> i_memop_sign_ext; // Load memory value with sign extending
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sc_in<sc_uint<2>> i_memop_size; // Memory transaction size
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sc_in<sc_uint<2>> i_memop_size; // Memory transaction size
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sc_in<bool> i_unsigned_op; // Unsigned operands
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sc_in<bool> i_unsigned_op; // Unsigned operands
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sc_in<bool> i_rv32; // 32-bits instruction
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sc_in<bool> i_rv32; // 32-bits instruction
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sc_in<bool> i_compressed; // C-extension (2-bytes length)
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sc_in<sc_bv<ISA_Total>> i_isa_type; // Type of the instruction's structure (ISA spec.)
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sc_in<sc_bv<ISA_Total>> i_isa_type; // Type of the instruction's structure (ISA spec.)
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sc_in<sc_bv<Instr_Total>> i_ivec; // One pulse per supported instruction.
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sc_in<sc_bv<Instr_Total>> i_ivec; // One pulse per supported instruction.
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sc_in<bool> i_ie; // Interrupt enable bit
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sc_in<bool> i_ie; // Interrupt enable bit
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_mtvec; // Interrupt descriptor table
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_mtvec; // Interrupt descriptor table
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sc_in<sc_uint<2>> i_mode; // Current processor mode
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sc_in<sc_uint<2>> i_mode; // Current processor mode
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