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URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_sysc_plugin/] [riverlib/] [core/] [proc.cpp] - Diff between revs 3 and 4

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Rev 3 Rev 4
Line 69... Line 69...
    dec0->o_memop_load(w.d.memop_load);
    dec0->o_memop_load(w.d.memop_load);
    dec0->o_memop_sign_ext(w.d.memop_sign_ext);
    dec0->o_memop_sign_ext(w.d.memop_sign_ext);
    dec0->o_memop_size(w.d.memop_size);
    dec0->o_memop_size(w.d.memop_size);
    dec0->o_unsigned_op(w.d.unsigned_op);
    dec0->o_unsigned_op(w.d.unsigned_op);
    dec0->o_rv32(w.d.rv32);
    dec0->o_rv32(w.d.rv32);
 
    dec0->o_compressed(w.d.compressed);
    dec0->o_isa_type(w.d.isa_type);
    dec0->o_isa_type(w.d.isa_type);
    dec0->o_instr_vec(w.d.instr_vec);
    dec0->o_instr_vec(w.d.instr_vec);
    dec0->o_exception(w.d.exception);
    dec0->o_exception(w.d.exception);
 
 
    exec0 = new InstrExecute("exec0");
    exec0 = new InstrExecute("exec0");
Line 87... Line 88...
    exec0->i_memop_load(w.d.memop_load);
    exec0->i_memop_load(w.d.memop_load);
    exec0->i_memop_sign_ext(w.d.memop_sign_ext);
    exec0->i_memop_sign_ext(w.d.memop_sign_ext);
    exec0->i_memop_size(w.d.memop_size);
    exec0->i_memop_size(w.d.memop_size);
    exec0->i_unsigned_op(w.d.unsigned_op);
    exec0->i_unsigned_op(w.d.unsigned_op);
    exec0->i_rv32(w.d.rv32);
    exec0->i_rv32(w.d.rv32);
 
    exec0->i_compressed(w.d.compressed);
    exec0->i_isa_type(w.d.isa_type);
    exec0->i_isa_type(w.d.isa_type);
    exec0->i_ivec(w.d.instr_vec);
    exec0->i_ivec(w.d.instr_vec);
    exec0->i_ie(csr.ie);
    exec0->i_ie(csr.ie);
    exec0->i_mtvec(csr.mtvec);
    exec0->i_mtvec(csr.mtvec);
    exec0->i_mode(csr.mode);
    exec0->i_mode(csr.mode);
Line 285... Line 287...
    fetch0->generateVCD(i_vcd, o_vcd);
    fetch0->generateVCD(i_vcd, o_vcd);
    mem0->generateVCD(i_vcd, o_vcd);
    mem0->generateVCD(i_vcd, o_vcd);
    iregs0->generateVCD(i_vcd, o_vcd);
    iregs0->generateVCD(i_vcd, o_vcd);
}
}
 
 
 
 
void Processor::comb() {
void Processor::comb() {
 
 
    w_fetch_pipeline_hold = w.e.pipeline_hold | w.m.pipeline_hold | dbg.halt;
    w_fetch_pipeline_hold = w.e.pipeline_hold | w.m.pipeline_hold | dbg.halt;
    w_any_pipeline_hold = w.f.pipeline_hold | w.e.pipeline_hold
    w_any_pipeline_hold = w.f.pipeline_hold | w.e.pipeline_hold
                        | w.m.pipeline_hold | dbg.halt;
                        | w.m.pipeline_hold | dbg.halt;
    w_exec_pipeline_hold = w.f.pipeline_hold | w.m.pipeline_hold | dbg.halt;
    w_exec_pipeline_hold = w.f.pipeline_hold | w.m.pipeline_hold | dbg.halt;
 
 
Line 321... Line 321...
        return;
        return;
    }
    }
    int sz;
    int sz;
    if (w.m.valid.read()) {
    if (w.m.valid.read()) {
        uint64_t line_cnt = dbg.executed_cnt.read() + 1;
        uint64_t line_cnt = dbg.executed_cnt.read() + 1;
        sz = RISCV_sprintf(tstr, sizeof(tstr), "%8" RV_PRI64 "d [%08x] %08x: ",
        sz = RISCV_sprintf(tstr, sizeof(tstr), "%8" RV_PRI64 "d [%08x]: ",
            line_cnt,
            line_cnt,
            w.m.pc.read().to_int(),
            w.m.pc.read().to_int());
            w.m.instr.read().to_int());
 
        uint64_t prev_val = iregs0->r.mem[w.w.waddr.read().to_int()].to_int64();
        uint64_t prev_val = iregs0->r.mem[w.w.waddr.read().to_int()].to_int64();
        uint64_t cur_val = w.w.wdata.read().to_int64();
        uint64_t cur_val = w.w.wdata.read().to_int64();
        if (w.w.waddr.read() == 0 || prev_val == cur_val) {
        if (w.w.waddr.read() == 0 || prev_val == cur_val) {
            // not writing
            // not writing
            sz += RISCV_sprintf(&tstr[sz], sizeof(tstr) - sz, "%s", "-\n");
            sz += RISCV_sprintf(&tstr[sz], sizeof(tstr) - sz, "%s", "-\n");

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