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/**
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/*
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* @file
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* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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*
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* Licensed under the Apache License, Version 2.0 (the "License");
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* @brief SystemC CPU wrapper. To interact with the SoC simulator.
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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*/
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#include "api_core.h"
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#include "api_core.h"
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#include "rtl_wrapper.h"
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#include "rtl_wrapper.h"
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#if 1
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#include "iservice.h"
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#include "iservice.h"
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#include <riscv-isa.h>
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#include "coreservices/iserial.h"
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#include "coreservices/iserial.h"
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#endif
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#include "coreservices/isocinfo.h"
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//#define SIMULATE_WAIT_STATES
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//#define SIMULATE_WAIT_STATES
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namespace debugger {
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namespace debugger {
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sensitive << r.wait_state_cnt;
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sensitive << r.wait_state_cnt;
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SC_METHOD(clk_negedge_proc);
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SC_METHOD(clk_negedge_proc);
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sensitive << o_clk.negedge_event();
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sensitive << o_clk.negedge_event();
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w_nrst = 0;
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w_nrst = 1;//0;
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v.nrst = 0;
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v.nrst = 1;//0;
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v.interrupt = false;
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v.interrupt = false;
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w_interrupt = 0;
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w_interrupt = 0;
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v.resp_mem_data = 0;
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v.resp_mem_data = 0;
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v.resp_mem_data_valid = false;
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v.resp_mem_data_valid = false;
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RISCV_event_create(&dport_.valid, "dport_valid");
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RISCV_event_create(&dport_.valid, "dport_valid");
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// todo: instead sc_clock
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// todo: instead sc_clock
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}
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}
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void RtlWrapper::comb() {
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void RtlWrapper::comb() {
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o_nrst = r.nrst.read()[1];
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o_nrst = r.nrst.read()[1].to_bool();
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o_resp_mem_data_valid = r.resp_mem_data_valid;
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o_resp_mem_data_valid = r.resp_mem_data_valid;
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o_resp_mem_data = r.resp_mem_data;
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o_resp_mem_data = r.resp_mem_data;
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o_interrupt = r.interrupt;
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o_interrupt = r.interrupt;
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#ifdef SIMULATE_WAIT_STATES
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#ifdef SIMULATE_WAIT_STATES
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if (r.wait_state_cnt.read() == 1) {
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if (r.wait_state_cnt.read() == 1) {
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step_queue_.pushPreQueued();
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step_queue_.pushPreQueued();
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uint64_t step_cnt = i_time.read();
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uint64_t step_cnt = i_time.read();
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while ((cb = step_queue_.getNext(step_cnt)) != 0) {
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while ((cb = step_queue_.getNext(step_cnt)) != 0) {
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static_cast<IClockListener *>(cb)->stepCallback(step_cnt);
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static_cast<IClockListener *>(cb)->stepCallback(step_cnt);
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}
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}
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if (generate_ref_ && step_cnt != step_cnt_z) {
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char msg[16];
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int msg_len = 0;
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IService *uart = NULL;
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switch (step_cnt) {
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case 22077:
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uart = static_cast<IService *>(RISCV_get_service("uart0"));
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msg[0] = 'h';
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msg_len = 1;
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break;
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case 22500:
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uart = static_cast<IService *>(RISCV_get_service("uart0"));
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msg[0] = 'e';
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msg[1] = 'l';
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msg_len = 2;
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break;
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case 24347:
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uart = static_cast<IService *>(RISCV_get_service("uart0"));
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msg[0] = 'p';
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msg[1] = '\r';
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msg[2] = '\n';
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msg_len = 3;
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break;
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default:;
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}
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if (uart) {
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ISerial *iserial = static_cast<ISerial *>(
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uart->getInterface(IFACE_SERIAL));
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iserial->writeData(msg, msg_len);
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}
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}
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step_cnt_z = i_time.read();
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/** */
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/** */
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v.interrupt = w_interrupt;
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v.interrupt = w_interrupt;
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v.nrst = (r.nrst.read() << 1) | w_nrst;
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v.nrst = (r.nrst.read() << 1) | w_nrst;
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v.wait_state_cnt = r.wait_state_cnt.read() + 1;
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v.wait_state_cnt = r.wait_state_cnt.read() + 1;
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if (RISCV_event_is_set(&dport_.valid)) {
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if (RISCV_event_is_set(&dport_.valid)) {
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RISCV_event_clear(&dport_.valid);
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RISCV_event_clear(&dport_.valid);
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v.dport_valid = 1;
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v.dport_valid = 1;
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v.dport_write = dport_.trans->write;
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v.dport_write = dport_.trans->write;
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v.dport_region = dport_.trans->region;
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v.dport_region = dport_.trans->region;
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v.dport_addr = dport_.trans->addr;
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v.dport_addr = dport_.trans->addr >> 3;
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v.dport_wdata = dport_.trans->wdata;
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v.dport_wdata = dport_.trans->wdata;
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}
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}
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dport_.idx_missmatch = 0;
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dport_.idx_missmatch = 0;
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if (i_dport_ready.read()) {
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if (i_dport_ready.read()) {
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dport_.trans->rdata = i_dport_rdata.read().to_uint64();
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dport_.trans->rdata = i_dport_rdata.read().to_uint64();
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}
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}
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}
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}
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void RtlWrapper::raiseSignal(int idx) {
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void RtlWrapper::raiseSignal(int idx) {
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switch (idx) {
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switch (idx) {
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case CPU_SIGNAL_RESET:
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case SIGNAL_HardReset:
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w_nrst = 0;
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w_nrst = 0;
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break;
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break;
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case CPU_SIGNAL_EXT_IRQ:
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case INTERRUPT_MExternal:
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w_interrupt = true;
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w_interrupt = true;
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break;
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break;
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default:;
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default:;
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}
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}
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}
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}
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void RtlWrapper::lowerSignal(int idx) {
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void RtlWrapper::lowerSignal(int idx) {
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switch (idx) {
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switch (idx) {
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case CPU_SIGNAL_RESET:
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case SIGNAL_HardReset:
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w_nrst = 1;
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w_nrst = 1;
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break;
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break;
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case CPU_SIGNAL_EXT_IRQ:
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case INTERRUPT_MExternal:
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w_interrupt = false;
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w_interrupt = false;
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break;
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break;
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default:;
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default:;
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}
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}
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}
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}
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