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/**
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/*
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* @file
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* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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*
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* Licensed under the Apache License, Version 2.0 (the "License");
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* @brief SystemC CPU wrapper. To interact with the SoC simulator. */
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __DEBUGGER_RTL_WRAPPER_H__
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#ifndef __DEBUGGER_RTL_WRAPPER_H__
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#define __DEBUGGER_RTL_WRAPPER_H__
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#define __DEBUGGER_RTL_WRAPPER_H__
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#include "async_tqueue.h"
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#include "async_tqueue.h"
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#include "coreservices/ibus.h"
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#include "coreservices/imemop.h"
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#include "coreservices/ireset.h"
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#include "coreservices/icpugen.h"
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#include "coreservices/icpuriscv.h"
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#include "coreservices/icpuriscv.h"
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#include "coreservices/iclklistener.h"
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#include "coreservices/iclklistener.h"
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#include "riverlib/river_cfg.h"
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#include "riverlib/river_cfg.h"
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#include <systemc.h>
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#include <systemc.h>
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#include "api_utils.h"
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#include "api_utils.h"
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namespace debugger {
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namespace debugger {
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class RtlWrapper : public sc_module,
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class RtlWrapper : public sc_module,
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public IResetListener,
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public ICpuGeneric,
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public ICpuRiscV {
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public ICpuRiscV {
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public:
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public:
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sc_clock o_clk;
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sc_clock o_clk;
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sc_out<bool> o_nrst;
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sc_out<bool> o_nrst;
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// Timer:
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// Timer:
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virtual ~RtlWrapper();
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virtual ~RtlWrapper();
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public:
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public:
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void generateRef(bool v) { generate_ref_ = v; }
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void generateRef(bool v) { generate_ref_ = v; }
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void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
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void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
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void setBus(IBus *v) { ibus_ = v; }
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void setBus(IMemoryOperation *v) { ibus_ = v; }
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/** Default time resolution 1 picosecond. */
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/** Default time resolution 1 picosecond. */
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void setClockHz(double hz);
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void setClockHz(double hz);
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/** ICpuRiscV interface */
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/** ICpuGeneric interface */
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virtual void registerStepCallback(IClockListener *cb, uint64_t t);
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virtual void raiseSignal(int idx);
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virtual void raiseSignal(int idx);
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virtual void lowerSignal(int idx);
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virtual void lowerSignal(int idx);
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virtual void nb_transport_debug_port(DebugPortTransactionType *trans,
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virtual void nb_transport_debug_port(DebugPortTransactionType *trans,
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IDbgNbResponse *cb);
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IDbgNbResponse *cb);
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/** IClock */
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virtual void registerStepCallback(IClockListener *cb, uint64_t t);
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/** IResetListener */
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virtual void reset(bool active) {
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o_nrst.write(!active);
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}
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private:
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private:
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IFace *getInterface(const char *name) { return iparent_; }
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IFace *getInterface(const char *name) { return iparent_; }
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uint64_t mask2offset(uint8_t mask);
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uint64_t mask2offset(uint8_t mask);
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uint32_t mask2size(uint8_t mask); // nask with removed offset
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uint32_t mask2size(uint8_t mask); // nask with removed offset
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private:
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private:
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IBus *ibus_;
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IMemoryOperation *ibus_;
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IFace *iparent_; // pointer on parent module object (used for logging)
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IFace *iparent_; // pointer on parent module object (used for logging)
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int clockCycles_; // default in [ps]
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int clockCycles_; // default in [ps]
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AsyncTQueueType step_queue_;
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ClockAsyncTQueueType step_queue_;
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uint64_t step_cnt_z;
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bool generate_ref_;
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bool generate_ref_;
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sc_uint<32> t_trans_idx_up;
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sc_uint<32> t_trans_idx_up;
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sc_uint<32> t_trans_idx_down;
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sc_uint<32> t_trans_idx_down;
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