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/**
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/*
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* @file
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* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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*
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* Licensed under the Apache License, Version 2.0 (the "License");
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* @brief System Bus class declaration (AMBA or whatever).
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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*/
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#include "api_core.h"
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#include <api_core.h>
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#include "bus.h"
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#include "bus.h"
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#include "coreservices/icpuriscv.h"
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#include "coreservices/icpugen.h"
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namespace debugger {
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namespace debugger {
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/** Class registration in the Core */
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/** Class registration in the Core */
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REGISTER_CLASS(Bus)
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REGISTER_CLASS(Bus)
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Bus::Bus(const char *name)
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Bus::Bus(const char *name)
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: IService(name) {
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: IService(name) {
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registerInterface(static_cast<IBus *>(this));
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registerInterface(static_cast<IMemoryOperation *>(this));
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registerAttribute("MapList", &listMap_);
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registerAttribute("DSU", &dsu_);
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listMap_.make_list(0);
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imap_.make_list(0);
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RISCV_mutex_init(&mutexBAccess_);
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RISCV_mutex_init(&mutexBAccess_);
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RISCV_mutex_init(&mutexNBAccess_);
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RISCV_mutex_init(&mutexNBAccess_);
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memset(info_, 0, sizeof(info_));
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idsu_ = 0;
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}
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}
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Bus::~Bus() {
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Bus::~Bus() {
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RISCV_mutex_destroy(&mutexBAccess_);
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RISCV_mutex_destroy(&mutexBAccess_);
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RISCV_mutex_destroy(&mutexNBAccess_);
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RISCV_mutex_destroy(&mutexNBAccess_);
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}
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}
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void Bus::postinitService() {
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void Bus::postinitService() {
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if (dsu_.is_string()) {
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idsu_ = static_cast<IDsuGeneric *>(
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RISCV_get_service_iface(dsu_.to_string(), IFACE_DSU_GENERIC));
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if (!idsu_) {
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RISCV_debug("Can't find IDsuGeneric interface %s",
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dsu_.to_string());
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}
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}
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IMemoryOperation *imem;
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IMemoryOperation *imem;
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for (unsigned i = 0; i < listMap_.size(); i++) {
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for (unsigned i = 0; i < listMap_.size(); i++) {
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const AttributeType &dev = listMap_[i];
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if (dev.is_string()) {
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imem = static_cast<IMemoryOperation *>(RISCV_get_service_iface(
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imem = static_cast<IMemoryOperation *>(RISCV_get_service_iface(
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listMap_[i].to_string(), IFACE_MEMORY_OPERATION));
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dev.to_string(), IFACE_MEMORY_OPERATION));
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if (imem == 0) {
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RISCV_error("Can't find slave device %s", dev.to_string());
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continue;
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}
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map(imem);
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} else if (dev.is_list() && dev.size() == 2) {
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const AttributeType &devname = dev[0u];
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const AttributeType &portname = dev[1];
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imem = static_cast<IMemoryOperation *>(
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RISCV_get_service_port_iface(devname.to_string(),
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portname.to_string(),
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IFACE_MEMORY_OPERATION));
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if (imem == 0) {
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if (imem == 0) {
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RISCV_error("Can't find slave device %s", listMap_[i].to_string());
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RISCV_error("Can't find slave device %s:%s",
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dev[0u].to_string(), dev[1].to_string());
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continue;
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continue;
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}
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}
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map(imem);
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map(imem);
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}
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}
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}
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AttributeType clks;
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AttributeType clks;
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RISCV_get_clock_services(&clks);
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RISCV_get_clock_services(&clks);
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if (clks.size()) {
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if (clks.size()) {
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iclk0_ = static_cast<IClock *>(clks[0u].to_iface());
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iclk0_ = static_cast<IClock *>(clks[0u].to_iface());
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} else {
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} else {
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RISCV_error("CPUs not found", NULL);
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RISCV_error("CPUs not found", NULL);
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}
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}
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}
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}
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void Bus::map(IMemoryOperation *imemop) {
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AttributeType t1(imemop);
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imap_.add_to_list(&t1);
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}
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ETransStatus Bus::b_transport(Axi4TransactionType *trans) {
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ETransStatus Bus::b_transport(Axi4TransactionType *trans) {
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IMemoryOperation *imem;
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bool unmapped = true;
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ETransStatus ret = TRANS_OK;
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ETransStatus ret = TRANS_OK;
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uint32_t sz;
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IMemoryOperation *memdev = 0;
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RISCV_mutex_lock(&mutexBAccess_);
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RISCV_mutex_lock(&mutexBAccess_);
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for (unsigned i = 0; i < imap_.size(); i++) {
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getMapedDevice(trans, &memdev, &sz);
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imem = static_cast<IMemoryOperation *>(imap_[i].to_iface());
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if (imem->getBaseAddress() <= trans->addr
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&& trans->addr < (imem->getBaseAddress() + imem->getLength())) {
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imem->b_transport(trans);
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if (memdev == 0) {
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unmapped = false;
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RISCV_error("[%" RV_PRI64 "d] Blocking request to unmapped address "
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break;
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/// @todo Check memory overlapping
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}
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}
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if (unmapped) {
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RISCV_error("[%" RV_PRI64 "d] Read from unmapped address "
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"%08" RV_PRI64 "x", iclk0_->getStepCounter(), trans->addr);
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"%08" RV_PRI64 "x", iclk0_->getStepCounter(), trans->addr);
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memset(trans->rpayload.b8, 0xFF, trans->xsize);
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memset(trans->rpayload.b8, 0xFF, trans->xsize);
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ret = TRANS_ERROR;
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ret = TRANS_ERROR;
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} else {
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} else {
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memdev->b_transport(trans);
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RISCV_debug("[%08" RV_PRI64 "x] => [%08x %08x]",
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RISCV_debug("[%08" RV_PRI64 "x] => [%08x %08x]",
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trans->addr,
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trans->addr,
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trans->rpayload.b32[1], trans->rpayload.b32[0]);
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trans->rpayload.b32[1], trans->rpayload.b32[0]);
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}
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}
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// Update Bus utilization counters:
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// Update Bus utilization counters:
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if (idsu_) {
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if (trans->action == MemAction_Read) {
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if (trans->action == MemAction_Read) {
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info_[trans->source_idx].r_cnt++;
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idsu_->incrementRdAccess(trans->source_idx);
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} else if (trans->action == MemAction_Write) {
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} else if (trans->action == MemAction_Write) {
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info_[trans->source_idx].w_cnt++;
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idsu_->incrementWrAccess(trans->source_idx);
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}
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}
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}
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RISCV_mutex_unlock(&mutexBAccess_);
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RISCV_mutex_unlock(&mutexBAccess_);
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return ret;
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return ret;
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}
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}
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ETransStatus Bus::nb_transport(Axi4TransactionType *trans,
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ETransStatus Bus::nb_transport(Axi4TransactionType *trans,
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IAxi4NbResponse *cb) {
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IAxi4NbResponse *cb) {
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IMemoryOperation *imem;
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bool unmapped = true;
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ETransStatus ret = TRANS_OK;
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ETransStatus ret = TRANS_OK;
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IMemoryOperation *memdev = 0;
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uint32_t sz;
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RISCV_mutex_lock(&mutexNBAccess_);
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RISCV_mutex_lock(&mutexNBAccess_);
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for (unsigned i = 0; i < imap_.size(); i++) {
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getMapedDevice(trans, &memdev, &sz);
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imem = static_cast<IMemoryOperation *>(imap_[i].to_iface());
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if (imem->getBaseAddress() <= trans->addr
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&& trans->addr < (imem->getBaseAddress() + imem->getLength())) {
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imem->nb_transport(trans, cb);
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unmapped = false;
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break;
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}
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}
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if (unmapped) {
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if (memdev == 0) {
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RISCV_error("[%" RV_PRI64 "d] Non-blocking request to unmapped address "
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RISCV_error("[%" RV_PRI64 "d] Non-blocking request to unmapped address "
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"%08" RV_PRI64 "x", iclk0_->getStepCounter(), trans->addr);
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"%08" RV_PRI64 "x", iclk0_->getStepCounter(), trans->addr);
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memset(trans->rpayload.b8, 0xFF, trans->xsize);
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memset(trans->rpayload.b8, 0xFF, trans->xsize);
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trans->response = MemResp_Error;
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trans->response = MemResp_Error;
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cb->nb_response(trans);
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cb->nb_response(trans);
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ret = TRANS_ERROR;
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ret = TRANS_ERROR;
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} else {
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} else {
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memdev->nb_transport(trans, cb);
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RISCV_debug("Non-blocking request to [%08" RV_PRI64 "x]",
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RISCV_debug("Non-blocking request to [%08" RV_PRI64 "x]",
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trans->addr);
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trans->addr);
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}
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}
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// Update Bus utilization counters:
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// Update Bus utilization counters:
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if (idsu_) {
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if (trans->action == MemAction_Read) {
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if (trans->action == MemAction_Read) {
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info_[trans->source_idx].r_cnt++;
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idsu_->incrementRdAccess(trans->source_idx);
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} else if (trans->action == MemAction_Write) {
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} else if (trans->action == MemAction_Write) {
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info_[trans->source_idx].w_cnt++;
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idsu_->incrementWrAccess(trans->source_idx);
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}
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}
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}
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RISCV_mutex_unlock(&mutexNBAccess_);
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RISCV_mutex_unlock(&mutexNBAccess_);
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return ret;
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return ret;
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}
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}
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BusUtilType *Bus::bus_utilization() {
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void Bus::getMapedDevice(Axi4TransactionType *trans,
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return info_;
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IMemoryOperation **pdev, uint32_t *sz) {
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IMemoryOperation *imem;
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uint64_t bar, barsz;
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*pdev = 0;
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*sz = 0;
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for (unsigned i = 0; i < imap_.size(); i++) {
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imem = static_cast<IMemoryOperation *>(imap_[i].to_iface());
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bar = imem->getBaseAddress();
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barsz = imem->getLength();
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if (bar <= trans->addr && trans->addr < (bar + barsz)) {
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if (!(*pdev) || imem->getPriority() > (*pdev)->getPriority()) {
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*pdev = imem;
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}
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}
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}
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}
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}
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} // namespace debugger
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} // namespace debugger
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No newline at end of file
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No newline at end of file
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