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* @brief Interrupt controller functional model.
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* @brief Interrupt controller functional model.
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*/
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*/
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#include "api_core.h"
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#include "api_core.h"
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#include "irqctrl.h"
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#include "irqctrl.h"
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#include <riscv-isa.h>
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#include "coreservices/icpuriscv.h"
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namespace debugger {
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namespace debugger {
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IrqPort::IrqPort(IService *parent, const char *portname, int idx) {
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parent_ = parent;
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parent->registerPortInterface(portname, static_cast<IWire *>(this));
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idx_ = idx;
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level_ = false;
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};
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void IrqPort::raiseLine() {
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level_ = true;
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static_cast<IrqController *>(parent_)->requestInterrupt(idx_);
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}
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void IrqPort::setLevel(bool level) {
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if (!level_ && level) {
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raiseLine();
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} else if (level_ && !level) {
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lowerLine();
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}
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}
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IrqController::IrqController(const char *name) : IService(name) {
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IrqController::IrqController(const char *name) : IService(name) {
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registerInterface(static_cast<IMemoryOperation *>(this));
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registerInterface(static_cast<IMemoryOperation *>(this));
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registerInterface(static_cast<IWire *>(this));
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registerInterface(static_cast<IClockListener *>(this));
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registerAttribute("BaseAddress", &baseAddress_);
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registerAttribute("Length", &length_);
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registerAttribute("CPU", &cpu_);
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registerAttribute("CPU", &cpu_);
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registerAttribute("CSR_MIPI", &mipi_);
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registerAttribute("CSR_MIPI", &mipi_);
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registerAttribute("IrqTotal", &irqTotal_);
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registerAttribute("IrqTotal", &irqTotal_);
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baseAddress_.make_uint64(0);
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char portname[256];
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for (int i = 1; i < IRQ_MAX; i++) {
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RISCV_sprintf(portname, sizeof(portname), "irq%d", i);
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irqlines_[i] = new IrqPort(this, portname, i);
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}
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mipi_.make_uint64(0x783);
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mipi_.make_uint64(0x783);
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length_.make_uint64(0);
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cpu_.make_string("");
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cpu_.make_string("");
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irqTotal_.make_uint64(4);
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irqTotal_.make_uint64(4);
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memset(®s_, 0, sizeof(regs_));
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memset(®s_, 0, sizeof(regs_));
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regs_.irq_mask = ~0;
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regs_.irq_mask = ~0;
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regs_.irq_lock = 1;
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regs_.irq_lock = 1;
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irq_wait_unlock = 0;
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}
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}
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IrqController::~IrqController() {
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IrqController::~IrqController() {
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}
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}
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void IrqController::postinitService() {
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void IrqController::postinitService() {
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icpu_ = static_cast<ICpuRiscV *>(
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iclk_ = static_cast<IClock *>(
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RISCV_get_service_iface(cpu_.to_string(), IFACE_CPU_RISCV));
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RISCV_get_service_iface(cpu_.to_string(), IFACE_CLOCK));
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if (!iclk_) {
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RISCV_error("Can't find IClock interface %s", cpu_.to_string());
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return;
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}
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icpu_ = static_cast<ICpuGeneric *>(
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RISCV_get_service_iface(cpu_.to_string(), IFACE_CPU_GENERIC));
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if (!icpu_) {
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if (!icpu_) {
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RISCV_error("Can't find ICpuRiscV interface %s", cpu_.to_string());
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RISCV_error("Can't find ICpuRiscV interface %s", cpu_.to_string());
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return;
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}
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}
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uint64_t t = iclk_->getStepCounter();
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iclk_->registerStepCallback(static_cast<IClockListener *>(this), t + 1);
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}
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}
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void IrqController::b_transport(Axi4TransactionType *trans) {
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ETransStatus IrqController::b_transport(Axi4TransactionType *trans) {
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uint64_t mask = (length_.to_uint64() - 1);
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uint64_t mask = (length_.to_uint64() - 1);
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uint64_t off = ((trans->addr - getBaseAddress()) & mask) / 4;
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uint64_t off = ((trans->addr - getBaseAddress()) & mask) / 4;
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uint32_t t1;
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uint32_t t1;
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trans->response = MemResp_Valid;
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trans->response = MemResp_Valid;
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if (trans->action == MemAction_Write) {
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if (trans->action == MemAction_Write) {
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break;
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break;
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case 2:
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case 2:
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t1 = regs_.irq_pending;
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t1 = regs_.irq_pending;
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regs_.irq_pending &= ~trans->wpayload.b32[i];
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regs_.irq_pending &= ~trans->wpayload.b32[i];
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if (t1 && !regs_.irq_pending) {
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if (t1 && !regs_.irq_pending) {
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icpu_->lowerSignal(CPU_SIGNAL_EXT_IRQ);
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icpu_->lowerSignal(INTERRUPT_MExternal);
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}
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}
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RISCV_info("Set irq_clear = %08x", trans->wpayload.b32[i]);
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RISCV_info("Set irq_clear = %08x", trans->wpayload.b32[i]);
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break;
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break;
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case 3:
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case 3:
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regs_.irq_pending |= trans->wpayload.b32[i];
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regs_.irq_pending |= trans->wpayload.b32[i];
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trans->wpayload.b32[i]);
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trans->wpayload.b32[i]);
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break;
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break;
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case 10:
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case 10:
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regs_.irq_lock = trans->wpayload.b32[i];
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regs_.irq_lock = trans->wpayload.b32[i];
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RISCV_info("Set irq_ena = %08x", trans->wpayload.b32[i]);
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RISCV_info("Set irq_ena = %08x", trans->wpayload.b32[i]);
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if (regs_.irq_lock == 0 && (regs_.irq_pending ||irq_wait_unlock)) {
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if (regs_.irq_lock == 0 && regs_.irq_pending) {
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regs_.irq_pending |= irq_wait_unlock;
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icpu_->lowerSignal(INTERRUPT_MExternal);
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icpu_->raiseSignal(CPU_SIGNAL_EXT_IRQ);
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irq_wait_unlock = 0;
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} else if (regs_.irq_lock == 1 && regs_.irq_pending) {
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icpu_->lowerSignal(CPU_SIGNAL_EXT_IRQ);
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}
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}
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break;
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break;
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case 11:
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case 11:
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regs_.irq_cause_idx = trans->wpayload.b32[i];
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regs_.irq_cause_idx = trans->wpayload.b32[i];
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RISCV_info("Set irq_cause_idx = %08x", trans->wpayload.b32[i]);
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RISCV_info("Set irq_cause_idx = %08x", trans->wpayload.b32[i]);
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default:
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default:
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trans->rpayload.b32[i] = ~0;
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trans->rpayload.b32[i] = ~0;
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}
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}
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}
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}
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}
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}
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return TRANS_OK;
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}
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}
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void IrqController::raiseLine(int idx) {
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void IrqController::stepCallback(uint64_t t) {
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if (regs_.irq_lock) {
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iclk_->registerStepCallback(static_cast<IClockListener *>(this), t + 1);
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irq_wait_unlock |= (~regs_.irq_mask & (1 << idx));
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if (regs_.irq_lock == 1) {
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return;
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return;
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}
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}
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if ((regs_.irq_mask & (0x1 << idx)) == 0) {
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if (~regs_.irq_mask & regs_.irq_pending) {
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regs_.irq_pending |= (0x1 << idx);
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icpu_->raiseSignal(INTERRUPT_MExternal); // PLIC interrupt (external)
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icpu_->raiseSignal(CPU_SIGNAL_EXT_IRQ); // PLIC interrupt (external)
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RISCV_debug("Raise interrupt", NULL);
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RISCV_info("Raise interrupt", NULL);
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}
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}
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}
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}
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void IrqController::requestInterrupt(int idx) {
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regs_.irq_pending |= (0x1 << idx);
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RISCV_info("request Interrupt %d", idx);
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}
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} // namespace debugger
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} // namespace debugger
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No newline at end of file
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No newline at end of file
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