| Line 23... |
Line 23... |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
*
|
*
|
* File: $Id: bin2vhd.c,v 1.1 2007-01-25 20:32:30 cwalter Exp $
|
* File: $Id: bin2vhd.c,v 1.2 2007-01-25 21:08:25 cwalter Exp $
|
*/
|
*/
|
|
|
#include <stdio.h>
|
#include <stdio.h>
|
#include <stdlib.h>
|
#include <stdlib.h>
|
#include <string.h>
|
#include <string.h>
|
| Line 113... |
Line 113... |
}
|
}
|
|
|
void
|
void
|
vWriteEntity( FILE * pxOutputFile )
|
vWriteEntity( FILE * pxOutputFile )
|
{
|
{
|
fprintf( pxOutputFile, "libary IEEE;\n" );
|
fprintf( pxOutputFile, "library IEEE;\n" );
|
fprintf( pxOutputFile, "use IEEE.STD_LOGIC_1164.all;\n" );
|
fprintf( pxOutputFile, "use IEEE.STD_LOGIC_1164.all;\n" );
|
fprintf( pxOutputFile, "use IEEE.NUMERIC_STD.all;\n" );
|
fprintf( pxOutputFile, "use IEEE.NUMERIC_STD.all;\n" );
|
fprintf( pxOutputFile, "entity %s is\n", VHDL_ENTITY_NAME );
|
fprintf( pxOutputFile, "entity %s is\n", VHDL_ENTITY_NAME );
|
fprintf( pxOutputFile, "port (\n" );
|
fprintf( pxOutputFile, "port (\n" );
|
fprintf( pxOutputFile, " clk : in std_logic;\n" );
|
fprintf( pxOutputFile, " clk : in std_logic;\n" );
|
fprintf( pxOutputFile, " addr : in std_logic_vector(%d downto 0 );\n", ( ADDRESS_BITS - 1 ) );
|
fprintf( pxOutputFile, " addr : in std_logic_vector(%d downto 0 );\n", ( ADDRESS_BITS - 1 ) );
|
fprintf( pxOutputFile, " data : out std_logic_vector(%d downto 0 ) );\n", ( DATA_BITS - 1 ) );
|
fprintf( pxOutputFile, " data : out std_logic_vector(%d downto 0 ) );\n", ( DATA_BITS - 1 ) );
|
fprintf( pxOutputFile, ")\n" );
|
fprintf( pxOutputFile, "end %s;\n", VHDL_ENTITY_NAME );
|
fprintf( pxOutputFile, "\n" );
|
fprintf( pxOutputFile, "\n" );
|
}
|
}
|
|
|
void
|
void
|
vWriteArchitectureHeader( FILE * pxOutputFile )
|
vWriteArchitectureHeader( FILE * pxOutputFile )
|
{
|
{
|
fprintf( pxOutputFile, "architecture %s of %s is\n", VHDL_ARCHITECTURE_NAME, VHDL_ENTITY_NAME );
|
fprintf( pxOutputFile, "architecture %s of %s is\n", VHDL_ARCHITECTURE_NAME, VHDL_ENTITY_NAME );
|
fprintf( pxOutputFile, " signal data_next : std_logic_vector(%d downto 0 ) );\n",
|
fprintf( pxOutputFile, " signal sig_data_next : std_logic_vector(%d downto 0 );\n",
|
( DATA_BITS - 1 ) );
|
( DATA_BITS - 1 ) );
|
if( IS_SYNCHRONOUS )
|
if( IS_SYNCHRONOUS )
|
{
|
{
|
fprintf( pxOutputFile, " signal data_int : std_logic_vector(%d downto 0 ) );\n",
|
fprintf( pxOutputFile, " signal sig_data_int : std_logic_vector(%d downto 0 ) );\n",
|
( DATA_BITS - 1 ) );
|
( DATA_BITS - 1 ) );
|
fprintf( pxOutputFile, "begin\n" );
|
fprintf( pxOutputFile, "begin\n" );
|
fprintf( pxOutputFile, " data <= signal_data_int\n" );
|
fprintf( pxOutputFile, " data <= sig_data_int\n" );
|
fprintf( pxOutputFile, "process (clk)\n" );
|
fprintf( pxOutputFile, "process (clk)\n" );
|
fprintf( pxOutputFile, " if clk'event and clk = '1' then\n" );
|
fprintf( pxOutputFile, " if clk'event and clk = '1' then\n" );
|
fprintf( pxOutputFile, " signal_data_int <= signal_data_next;\n" );
|
fprintf( pxOutputFile, " sig_data_int <= sig_data_next;\n" );
|
fprintf( pxOutputFile, " end if;\n" );
|
fprintf( pxOutputFile, " end if;\n" );
|
fprintf( pxOutputFile, "end process;\n" );
|
fprintf( pxOutputFile, "end process;\n" );
|
}
|
}
|
else
|
else
|
{
|
{
|
fprintf( pxOutputFile, "begin\n" );
|
fprintf( pxOutputFile, "begin\n" );
|
fprintf( pxOutputFile, " data <= signal_data_next\n" );
|
fprintf( pxOutputFile, " data <= sig_data_next;\n" );
|
}
|
}
|
fprintf( pxOutputFile, "\n" );
|
fprintf( pxOutputFile, "\n" );
|
fprintf( pxOutputFile, " process( addr )\n" );
|
fprintf( pxOutputFile, " process( addr )\n" );
|
fprintf( pxOutputFile, " begin\n" );
|
fprintf( pxOutputFile, " begin\n" );
|
fprintf( pxOutputFile, " case addr is\n" );
|
fprintf( pxOutputFile, " case addr is\n" );
|
| Line 167... |
Line 167... |
{
|
{
|
for( i = 0; i < ( DATA_BITS / 4 ); i += 2, iBytePos++ )
|
for( i = 0; i < ( DATA_BITS / 4 ); i += 2, iBytePos++ )
|
{
|
{
|
sprintf( &arucBuffer[i], "%02X", pucData[iBytePos] );
|
sprintf( &arucBuffer[i], "%02X", pucData[iBytePos] );
|
}
|
}
|
fprintf( pxOutputFile, " when x\"%s\" => signal_data_next <= x\"%*s\"\n",
|
fprintf( pxOutputFile, " when x\"%s\" => sig_data_next <= x\"%*s\";\n",
|
pcAddress2Hex( uiProgrammCounter ), DATA_BITS / 4, arucBuffer );
|
pcAddress2Hex( uiProgrammCounter ), DATA_BITS / 4, arucBuffer );
|
uiProgrammCounter += PC_INCREMENT;
|
uiProgrammCounter += PC_INCREMENT;
|
}
|
}
|
}
|
}
|
|
|
void
|
void
|
vWriteArchitectureFooter( FILE * pxOutputFile )
|
vWriteArchitectureFooter( FILE * pxOutputFile )
|
{
|
{
|
fprintf( pxOutputFile, " when others => signal_data_next <= ( others => '0' );\n" );
|
fprintf( pxOutputFile, " when others => sig_data_next <= ( others => '0' );\n" );
|
fprintf( pxOutputFile, " end case;\n" );
|
fprintf( pxOutputFile, " end case;\n" );
|
fprintf( pxOutputFile, " end process;\n" );
|
fprintf( pxOutputFile, " end process;\n" );
|
fprintf( pxOutputFile, "\n" );
|
fprintf( pxOutputFile, "\n" );
|
fprintf( pxOutputFile, "end %s", VHDL_ARCHITECTURE_NAME );
|
fprintf( pxOutputFile, "end %s;", VHDL_ARCHITECTURE_NAME );
|
}
|
}
|
|
|
const char *
|
const char *
|
pcAddress2Hex( unsigned int uiHexValue )
|
pcAddress2Hex( unsigned int uiHexValue )
|
{
|
{
|
