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https://opencores.org/ocsvn/rise/rise/trunk
[/] [rise/] [trunk/] [vhdl/] [ex_stage.vhd] - Diff between revs 8 and 71
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Rev 71 |
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.std_logic_signed.all;
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use IEEE.std_logic_signed.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use WORK.RISE_PACK.all;
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use WORK.RISE_PACK.all;
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use work.RISE_PACK_SPECIFIC.all;
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entity ex_stage is
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entity ex_stage is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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