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-- Description:
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-- Description:
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-- Instruction decode stage
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-- Instruction decode stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.numeric_std.all;
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use WORK.RISE_PACK.all;
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use WORK.RISE_PACK.all;
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entity id_stage is
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entity id_stage is
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Line 42... |
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end id_stage;
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end id_stage;
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architecture id_stage_rtl of id_stage is
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architecture id_stage_rtl of id_stage is
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signal rx_addr_int : REGISTER_ADDR_T;
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signal ry_addr_int : REGISTER_ADDR_T;
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signal rz_addr_int : REGISTER_ADDR_T;
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signal id_ex_register_int : ID_EX_REGISTER_T;
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signal id_ex_register_int : ID_EX_REGISTER_T;
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signal id_ex_register_next : ID_EX_REGISTER_T;
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signal id_ex_register_next : ID_EX_REGISTER_T;
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function opcode_modifies_rx( opcode: in OPCODE_T ) return std_logic is
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function opcode_modifies_rx( opcode: in OPCODE_T ) return std_logic is
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variable modifies : std_logic;
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variable modifies : std_logic;
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begin
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begin
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case opcode is
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case opcode is
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when OPCODE_LD_IMM => modifies := '1';
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when OPCODE_JMP => modifies := '0';
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when others => modifies := '0';
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when OPCODE_TST => modifies := '0';
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when OPCODE_NOP => modifies := '0';
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when OPCODE_ST_DISP => modifies := '0';
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when others => modifies := '1';
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end case;
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end case;
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return modifies;
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return modifies;
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end;
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end;
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function register_is_ready( reg_addr: in REGISTER_ADDR_T ) return std_logic is
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variable index : integer range 0 to REGISTER_COUNT - 1;
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begin
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return '1';
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end;
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begin -- id_stage_rtl
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begin -- id_stage_rtl
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rx_addr <= rx_addr_int;
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ry_addr <= ry_addr_int;
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rz_addr <= rz_addr_int;
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id_ex_register <= id_ex_register_int;
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id_ex_register <= id_ex_register_int;
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-- process (clk, reset)
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-- process (clk, reset)
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-- begin -- process
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-- begin -- process
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-- if reset = '0' then -- asynchronous reset (active low)
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-- if reset = '0' then -- asynchronous reset (active low)
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| Line 95... |
Line 97... |
end if;
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end if;
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end process;
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end process;
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-- The opc_extender decodes the two different formats used for the opcodes
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-- The opc_extender decodes the two different formats used for the opcodes
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-- in the instruction set into a single 5-bit opcode format.
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-- in the instruction set into a single 5-bit opcode format.
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opc_extender: process (clk, reset )
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opc_extender: process ( clk, reset, if_id_register )
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begin
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begin
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if reset = '0' then
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if reset = '0' then
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id_ex_register_next.opcode <= OPCODE_NOP;
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id_ex_register_next.opcode <= OPCODE_NOP;
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-- decodes: OPCODE_LD_IMM, OPCODE_LD_IMM_HB
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-- decodes: OPCODE_LD_IMM, OPCODE_LD_IMM_HB
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elsif if_id_register.ir( 15 downto 13 ) = "100" then
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elsif if_id_register.ir( 15 downto 13 ) = "100" then
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Line 113... |
else
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else
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id_ex_register_next.opcode <= if_id_register.ir( 15 downto 11 );
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id_ex_register_next.opcode <= if_id_register.ir( 15 downto 11 );
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end if;
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end if;
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end process;
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end process;
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cond_decode: process (clk, reset )
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cond_decode: process ( clk, reset, if_id_register )
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begin
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begin
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if reset = '0' then
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if reset = '0' then
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id_ex_register_next.cond <= COND_NONE;
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id_ex_register_next.cond <= COND_NONE;
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-- decodes: OPCODE_LD_IMM, OPCODE_LD_IMM_HB
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-- decodes: OPCODE_LD_IMM, OPCODE_LD_IMM_HB
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elsif if_id_register.ir( 15 downto 13 ) = "100" then
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elsif if_id_register.ir( 15 downto 13 ) = "100" then
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id_ex_register_next.cond <= COND_UNCONDITIONAL;
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id_ex_register_next.cond <= COND_UNCONDITIONAL;
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-- decodes: OPCODE_LD_DISP, OPCODE_LD_DISP_MS, OPCODE_ST_DISP
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-- decodes: OPCODE_LD_DISP, OPCODE_LD_DISP_MS, OPCODE_ST_DISP
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elsif if_id_register.ir(15) = '1' then
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elsif if_id_register.ir(15) = '1' then
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id_ex_register_next.cond <= if_id_register.ir( 15 downto 13 );
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id_ex_register_next.cond <= if_id_register.ir( 12 downto 10 );
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-- decodes: OPCODE_XXX
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-- decodes: OPCODE_XXX
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else
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else
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id_ex_register_next.cond <= if_id_register.ir( 10 downto 8 );
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id_ex_register_next.cond <= if_id_register.ir( 10 downto 8 );
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end if;
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end if;
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end process;
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end process;
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pc: process( if_id_register )
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pc: process( reset, if_id_register )
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begin
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begin
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if reset = '0' then
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if reset = '0' then
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id_ex_register_next.pc <= RESET_PC_VALUE;
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id_ex_register_next.pc <= RESET_PC_VALUE;
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else
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else
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id_ex_register_next.pc <= if_id_register.pc;
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id_ex_register_next.pc <= if_id_register.pc;
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end if;
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end if;
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end process;
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end process;
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rx_decode_and_fetch: process (reset, if_id_register, id_ex_register_next)
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rx_decode_and_fetch: process ( reset, if_id_register, id_ex_register_next, rx)
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begin
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begin
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-- make sure we don't synthesize a latch for rx_addr
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-- make sure we don't synthesize a latch for rx_addr
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rx_addr <= ( others => '0' );
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rx_addr_int <= ( others => '0' );
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if reset = '0' then
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if reset = '0' then
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id_ex_register_next.rX <= ( others => '0' );
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id_ex_register_next.rX <= ( others => '0' );
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id_ex_register_next.rX_addr <= ( others => '0' );
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id_ex_register_next.rX_addr <= ( others => '0' );
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elsif id_ex_register_next.opcode = OPCODE_LD_IMM or
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elsif id_ex_register_next.opcode = OPCODE_LD_IMM or
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id_ex_register_next.opcode = OPCODE_LD_IMM_HB then
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id_ex_register_next.opcode = OPCODE_LD_IMM_HB then
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rx_addr <= if_id_register.ir( 11 downto 8 );
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rx_addr_int <= if_id_register.ir( 11 downto 8 );
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id_ex_register_next.rX <= rx;
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id_ex_register_next.rX <= rx;
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id_ex_register_next.rX_addr <= if_id_register.ir( 11 downto 8 );
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id_ex_register_next.rX_addr <= if_id_register.ir( 11 downto 8 );
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else
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else
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rx_addr <= if_id_register.ir( 7 downto 4 );
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rx_addr_int <= if_id_register.ir( 7 downto 4 );
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id_ex_register_next.rX <= rx;
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id_ex_register_next.rX <= rx;
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id_ex_register_next.rX_addr <= if_id_register.ir( 7 downto 4 );
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id_ex_register_next.rX_addr <= if_id_register.ir( 7 downto 4 );
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end if;
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end if;
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if opcode_modifies_rx( id_ex_register_next.opcode ) = '1' then
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if opcode_modifies_rx( id_ex_register_next.opcode ) = '1' then
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Line 166... |
lock_reg_addr <= ( others => '0' );
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lock_reg_addr <= ( others => '0' );
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set_reg_lock <= '0';
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set_reg_lock <= '0';
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end if;
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end if;
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end process;
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end process;
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ry_decode_and_fetch: process (reset, if_id_register, id_ex_register_next)
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ry_decode_and_fetch: process ( reset, if_id_register, id_ex_register_next, ry )
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begin
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begin
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-- make sure we don't synthesize a latch for ry_addr
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-- make sure we don't synthesize a latch for ry_addr_int
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ry_addr <= ( others => '0' );
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ry_addr_int <= ( others => '0' );
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if reset = '0' then
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if reset = '0' then
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id_ex_register_next.rY <= ( others => '0' );
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id_ex_register_next.rY <= ( others => '0' );
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else
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else
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ry_addr <= if_id_register.ir( 3 downto 0 );
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ry_addr_int <= if_id_register.ir( 3 downto 0 );
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id_ex_register_next.rZ <= rz;
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id_ex_register_next.rY <= ry;
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end if;
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end if;
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end process;
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end process;
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rz_decode_and_fetch: process (reset, if_id_register, id_ex_register_next)
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rz_decode_and_fetch: process ( reset, if_id_register, id_ex_register_next, rz )
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begin
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begin
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-- make sure we don't synthesize a latch for rz_addr
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-- make sure we don't synthesize a latch for rz_addr_int
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rz_addr <= ( others => '0' );
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rz_addr_int <= ( others => '0' );
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if reset = '0' then
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if reset = '0' then
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id_ex_register_next.rZ <= ( others => '0' );
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id_ex_register_next.rZ <= ( others => '0' );
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else
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else
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-- only the lower 2-bits of rz are encoded in the instruction
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-- only the lower 2-bits of rz are encoded in the instruction
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rz_addr <= "00" & if_id_register.ir( 9 downto 8 );
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rz_addr_int <= "00" & if_id_register.ir( 9 downto 8 );
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id_ex_register_next.rZ <= rz;
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id_ex_register_next.rZ <= rz;
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end if;
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end if;
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end process;
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end process;
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-- The immediate fetch process checks for all opcodes needing constants
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-- The immediate fetch process checks for all opcodes needing constants
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Line 212... |
when others =>
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when others =>
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id_ex_register_next.immediate <= x"000" & if_id_register.ir( 3 downto 0 );
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id_ex_register_next.immediate <= x"000" & if_id_register.ir( 3 downto 0 );
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end case;
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end case;
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end process;
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end process;
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-- Check if all registers are available. If not stall the pipeline.
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lock: process( reset, id_ex_register_next, rx_addr_int, ry_addr_int, rz_addr_int, lock_register )
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variable required: LOCK_REGISTER_T;
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begin
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required := ( others => '0' );
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if id_ex_register_next.cond /= COND_UNCONDITIONAL then
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required( TO_INTEGER( UNSIGNED( SR_REGISTER_ADDR ) ) ) := '1';
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end if;
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case id_ex_register_next.opcode is
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when OPCODE_LD_DISP =>
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required( TO_INTEGER( UNSIGNED( rz_addr_int ) ) ) := '1';
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_LD_DISP_MS =>
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required( TO_INTEGER( UNSIGNED( rz_addr_int ) ) ) := '1';
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_LD_REG =>
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_ST_DISP =>
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required( TO_INTEGER( UNSIGNED( rx_addr_int ) ) ) := '1';
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required( TO_INTEGER( UNSIGNED( rz_addr_int ) ) ) := '1';
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_ADD =>
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_SUB =>
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_NEG =>
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_ARS =>
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_ALS =>
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_AND =>
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_NOT =>
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_EOR =>
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_LS =>
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_RS =>
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required( TO_INTEGER( UNSIGNED( ry_addr_int ) ) ) := '1';
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when OPCODE_JMP =>
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required( TO_INTEGER( UNSIGNED( rx_addr_int ) ) ) := '1';
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when OPCODE_TST =>
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required( TO_INTEGER( UNSIGNED( rx_addr_int ) ) ) := '1';
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when others => null;
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end case;
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-- no checks if all registers are not locked.
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stall_out <= '0';
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if ( required & lock_register ) /= x"0000" then
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stall_out <= '1';
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end if;
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end process;
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end id_stage_rtl;
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end id_stage_rtl;
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No newline at end of file
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No newline at end of file
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