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[/] [rise/] [trunk/] [vhdl/] [id_stage.vhd] - Diff between revs 59 and 63

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Rev 59 Rev 63
Line 170... Line 170...
  end process;
  end process;
 
 
  -- The SR fetch process read the value of the SR registers and passes it to
  -- The SR fetch process read the value of the SR registers and passes it to
  -- the execute pipeline. In addition it checks if the opcode modifies the
  -- the execute pipeline. In addition it checks if the opcode modifies the
  -- SR register and if yes locks the register.
  -- SR register and if yes locks the register.
  sr_fetch : process (reset, sr, id_ex_register_next)
  sr_fetch : process (reset, sr, id_ex_register_next, stall_out_int )
  begin
  begin
    if reset = '0' then
    if reset = '0' then
      id_ex_register_next.sr <= RESET_SR_VALUE;
      id_ex_register_next.sr <= RESET_SR_VALUE;
    else
    else
      id_ex_register_next.sr <= sr;
      id_ex_register_next.sr <= sr;
Line 187... Line 187...
      lock_reg_addr1 <= (others => '-');
      lock_reg_addr1 <= (others => '-');
      set_reg_lock1  <= '0';
      set_reg_lock1  <= '0';
    end if;
    end if;
  end process;
  end process;
 
 
  rx_decode_and_fetch : process (reset, if_id_register, id_ex_register_next, rx )
  rx_decode_and_fetch : process (reset, if_id_register, id_ex_register_next, rx, stall_out_int )
  begin
  begin
    -- make sure we don't synthesize a latch for rx_addr
    -- make sure we don't synthesize a latch for rx_addr
    rx_addr_int <= (others => '0');
    rx_addr_int <= (others => '0');
 
 
    if reset = '0' then
    if reset = '0' then
Line 209... Line 209...
    end if;
    end if;
 
 
    if opcode_modifies_rx(id_ex_register_next.opcode) = '1' and stall_out_int = '0' then
    if opcode_modifies_rx(id_ex_register_next.opcode) = '1' and stall_out_int = '0' then
      lock_reg_addr0 <= id_ex_register_next.rX_addr;
      lock_reg_addr0 <= id_ex_register_next.rX_addr;
      set_reg_lock0  <= '1';
      set_reg_lock0  <= '1';
 
    elsif id_ex_register_next.opcode = OPCODE_JMP then
 
      lock_reg_addr0 <= LR_REGISTER_ADDR;
 
      set_reg_lock0  <= '1';
    else
    else
      lock_reg_addr0 <= (others => '-');
      lock_reg_addr0 <= (others => '-');
      set_reg_lock0  <= '0';
      set_reg_lock0  <= '0';
    end if;
    end if;
  end process;
  end process;

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