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Line 1... |
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
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(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
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(status (written (timeStamp 2007 1 10 0 54 20)
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(status (written (timeStamp 2007 1 14 14 42 55)
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(author "Xilinx, Inc.")
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(author "Xilinx, Inc.")
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(program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.1.03i"))))
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(program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.1.03i"))))
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(comment "
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(comment "
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This file is owned and controlled by Xilinx and must be used
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This file is owned and controlled by Xilinx and must be used
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solely for design, simulation, implementation and creation of
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solely for design, simulation, implementation and creation of
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(comment "c_ysinit_is_high = 0 ")
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(comment "c_ysinit_is_high = 0 ")
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(comment "c_ywe_is_high = 1 ")
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(comment "c_ywe_is_high = 1 ")
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(comment "c_yprimitive_type = 8kx2 ")
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(comment "c_yprimitive_type = 8kx2 ")
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(comment "c_ytop_addr = 1024 ")
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(comment "c_ytop_addr = 1024 ")
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(comment "c_yhierarchy = hierarchy1 ")
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(comment "c_yhierarchy = hierarchy1 ")
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(comment "c_has_limit_data_pitch = 0 ")
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(comment "c_has_limit_data_pitch = 1 ")
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(comment "c_has_rdy = 0 ")
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(comment "c_has_rdy = 0 ")
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(comment "c_write_mode = 0 ")
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(comment "c_write_mode = 0 ")
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(comment "c_width = 16 ")
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(comment "c_width = 16 ")
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(comment "c_yuse_single_primitive = 0 ")
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(comment "c_yuse_single_primitive = 0 ")
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(comment "c_has_nd = 0 ")
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(comment "c_has_nd = 0 ")
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