| Line 55... |
Line 55... |
--end if_stage_rtl;
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--end if_stage_rtl;
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-- This is a simple hardcoded IF unit for the RISE processor. It does not
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-- This is a simple hardcoded IF unit for the RISE processor. It does not
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-- use the memory and contains a hardcoded programm.
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-- use the memory and contains a hardcoded programm.
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architecture if_state_behavioral of if_stage is
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architecture if_state_behavioral of if_stage is
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signal if_id_register_int : IF_ID_REGISTER_T;
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signal if_id_register_int : IF_ID_REGISTER_T := ( others => ( others => '0' ) );
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signal if_id_register_next : IF_ID_REGISTER_T;
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signal if_id_register_next : IF_ID_REGISTER_T := ( others => ( others => '0' ) );
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begin
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begin
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if_id_register <= if_id_register_int;
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if_id_register <= if_id_register_int;
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process (clk, reset, clear_in)
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process (clk, reset, clear_in)
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| Line 77... |
Line 77... |
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process (reset, branch, branch_target, pc, clear_in)
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process (reset, branch, branch_target, pc, clear_in)
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begin
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begin
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if reset = '0' or clear_in = '1' then
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if reset = '0' or clear_in = '1' then
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if_id_register_next.pc <= PC_RESET_VECTOR;
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if_id_register_next.pc <= PC_RESET_VECTOR;
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pc_next <= PC_RESET_VECTOR;
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else
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else
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if_id_register_next.pc <= pc;
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if_id_register_next.pc <= pc;
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if branch = '1' then
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if branch = '1' then
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pc_next <= branch_target;
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pc_next <= branch_target;
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else
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else
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