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[/] [rise/] [trunk/] [vhdl/] [if_stage.vhd] - Diff between revs 45 and 50
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| Rev 45 |
Rev 50 |
| Line 80... |
Line 80... |
if reset = '0' or clear_in = '1' then
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if reset = '0' or clear_in = '1' then
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if_id_register_next.pc <= PC_RESET_VECTOR;
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if_id_register_next.pc <= PC_RESET_VECTOR;
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pc_next <= PC_RESET_VECTOR;
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pc_next <= PC_RESET_VECTOR;
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else
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else
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if_id_register_next.pc <= pc;
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if_id_register_next.pc <= pc;
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if stall_in = '0' then
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if branch = '1' then
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if branch = '1' then
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pc_next <= branch_target;
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pc_next <= branch_target;
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else
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else
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pc_next <= std_logic_vector(unsigned(pc) + 2);
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pc_next <= std_logic_vector(unsigned(pc) + 2);
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end if;
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end if;
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else
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pc_next <= pc;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- 00000000 <reset>:
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-- 0: 81 03 ld R1,#0x3
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-- 2: 91 01 ldhb R1,#0x1
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-- 4: 82 30 ld R2,#0x30
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-- 6: 82 33 ld R2,#0x33
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-- 8: 10 12 add R1,R2
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-- a: 88 00 ld R8,#0x0
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-- c: 98 00 ldhb R8,#0x0
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-- e: 70 08 jmp R8
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process (pc)
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process (pc)
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begin
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begin
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case pc is
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case pc is
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when x"0000" => if_id_register_next.ir <= x"8012"; -- ld r0, #0x12
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when x"0000" => if_id_register_next.ir <= x"8103"; -- ld R1,#0x3
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when x"0002" => if_id_register_next.ir <= x"8d01"; -- ld r5, #0x01
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when x"0002" => if_id_register_next.ir <= x"9101"; -- ldhb R1,#0x1
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when others => if_id_register_next.ir <= x"0000";
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when x"0004" => if_id_register_next.ir <= x"8230"; -- ld R2,#0x30
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when x"0006" => if_id_register_next.ir <= x"8233"; -- ld R2,#0x33
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when x"0008" => if_id_register_next.ir <= x"1012"; -- add R1,R2
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when x"000A" => if_id_register_next.ir <= x"8800"; -- ld R8,#0x0
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when x"000C" => if_id_register_next.ir <= x"9800"; -- ldhb R8,#0x0
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when x"7008" => if_id_register_next.ir <= x"7008"; -- jmp R8
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when others => if_id_register_next.ir <= x"0000"; -- nop
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end case;
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end case;
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end process;
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end process;
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end if_state_behavioral;
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end if_state_behavioral;
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