URL
https://opencores.org/ocsvn/rise/rise/trunk
[/] [rise/] [trunk/] [vhdl/] [imem.vhd] - Diff between revs 37 and 60
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 37 |
Rev 60 |
| Line 25... |
Line 25... |
data_out : out MEM_DATA_T);
|
data_out : out MEM_DATA_T);
|
|
|
end imem;
|
end imem;
|
|
|
architecture imem_rtl of imem is
|
architecture imem_rtl of imem is
|
|
|
component idmem
|
component idmem
|
port (
|
port (
|
addr: IN std_logic_VECTOR(11 downto 0);
|
addr: IN std_logic_VECTOR(11 downto 0);
|
clk: IN std_logic;
|
clk: IN std_logic;
|
din: IN std_logic_VECTOR(15 downto 0);
|
din: IN std_logic_VECTOR(15 downto 0);
|
dout: OUT std_logic_VECTOR(15 downto 0);
|
dout: OUT std_logic_VECTOR(15 downto 0);
|
sinit: IN std_logic;
|
sinit: IN std_logic;
|
we: IN std_logic);
|
we: IN std_logic);
|
end component;
|
end component;
|
|
|
|
|
begin -- imem_rtl
|
begin -- imem_rtl
|
|
|
INSTRUCTION_MEM : idmem
|
INSTRUCTION_MEM : idmem
|
port map (
|
port map (
|
addr => addr(11 downto 0),
|
addr => addr(11 downto 0),
|
clk => clk,
|
clk => clk,
|
din => data_in,
|
din => data_in,
|
dout => data_out,
|
dout => data_out,
|
sinit => reset,
|
sinit => reset,
|
we => wr_enable);
|
we => wr_enable);
|
|
|
end imem_rtl;
|
end imem_rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.