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Line 38... |
architecture mem_stage_rtl of mem_stage is
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architecture mem_stage_rtl of mem_stage is
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signal mem_wb_register_int : MEM_WB_REGISTER_T;
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signal mem_wb_register_int : MEM_WB_REGISTER_T;
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signal mem_wb_register_next : MEM_WB_REGISTER_T;
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signal mem_wb_register_next : MEM_WB_REGISTER_T;
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component sc_uart is
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generic (ADDR_BITS : integer;
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CLK_FREQ : integer;
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BAUD_RATE : integer;
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TXF_DEPTH : integer;
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TXF_THRES : integer;
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RXF_DEPTH : integer;
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RXF_THRES : integer);
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port (CLK : in std_logic;
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RESET : in std_logic;
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ADDRESS : in std_logic_vector(addr_bits-1 downto 0);
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WR_DATA : in std_logic_vector(15 downto 0);
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RD, WR : in std_logic;
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RD_DATA : out std_logic_vector(15 downto 0);
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RDY_CNT : out IEEE.NUMERIC_STD.unsigned(1 downto 0);
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TXD : out std_logic;
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RXD : in std_logic;
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NCTS : in std_logic;
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NRTS : out std_logic);
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end component;
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begin -- mem_stage_rtl
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begin -- mem_stage_rtl
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-- Uart modul einbinden
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UART : sc_uart generic map (
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ADDR_BITS => 2,
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CLK_FREQ => CLK_FREQ,
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BAUD_RATE => 115200,
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TXF_DEPTH => 2,
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TXF_THRES => 1,
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RXF_DEPTH => 2,
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RXF_THRES => 1
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)
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port map(
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CLK => clk,
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RESET => reset,
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ADDRESS => address(1 downto 0),
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WR_DATA => wr_data,
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RD => rd,
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WR => wr,
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RD_DATA => rd_data,
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RDY_CNT => rdy_cnt,
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TXD => txd,
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RXD => rxd,
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NCTS => '0',
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NRTS => open
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);
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mem_wb_register.aluop1 <= mem_wb_register_int.aluop1;
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mem_wb_register.aluop1 <= mem_wb_register_int.aluop1;
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mem_wb_register.aluop2 <= mem_wb_register_int.aluop2;
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mem_wb_register.aluop2 <= mem_wb_register_int.aluop2;
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mem_wb_register.reg <= mem_wb_register_int.reg;
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mem_wb_register.reg <= mem_wb_register_int.reg;
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mem_wb_register.mem_reg <= dmem_data_in;
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mem_wb_register.mem_reg <= dmem_data_in;
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| Line 59... |
Line 105... |
mem_wb_register_int.aluop2 <= (others => '0');
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mem_wb_register_int.aluop2 <= (others => '0');
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mem_wb_register_int.reg <= (others => '0');
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mem_wb_register_int.reg <= (others => '0');
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mem_wb_register_int.dreg_addr <= (others => '0');
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mem_wb_register_int.dreg_addr <= (others => '0');
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mem_wb_register_int.lr <= (others => '0');
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mem_wb_register_int.lr <= (others => '0');
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mem_wb_register_int.sr <= (others => '0');
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mem_wb_register_int.sr <= (others => '0');
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-- uart reset
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rd <= '0';
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wr <= '0';
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wr_data <= (others => 'X');
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rd_data <= (others => '0');
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address <= (others => 'X');
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elsif clk'event and clk = '1' then -- rising clock edge
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elsif clk'event and clk = '1' then -- rising clock edge
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mem_wb_register_int <= mem_wb_register_next;
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mem_wb_register_int <= mem_wb_register_next;
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end if;
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end if;
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end process;
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end process;
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Line 136... |
mem_wb_register_next.sr <= (others => '-');
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mem_wb_register_next.sr <= (others => '-');
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else
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else
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-- check if the instruction accesses the memory. if yes then
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-- check if the instruction accesses the memory. if yes then
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-- either load or store data from the memory.
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-- either load or store data from the memory.
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assert ex_mem_register.aluop1(ALUOP1_LD_MEM_BIT) = '0' or ex_mem_register.aluop1(ALUOP1_ST_MEM_BIT) = '0';
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assert ex_mem_register.aluop1(ALUOP1_LD_MEM_BIT) = '0' or ex_mem_register.aluop1(ALUOP1_ST_MEM_BIT) = '0';
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--load from mem
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if ex_mem_register.aluop1(ALUOP1_LD_MEM_BIT) = '1' then
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if ex_mem_register.aluop1(ALUOP1_LD_MEM_BIT) = '1' then
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dmem_addr <= ex_mem_register.alu;
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if ex_mem_register.alu = CONST_ADDRESS then
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--load from UART
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address <= CONDT_ADDRESS;
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rd ='1';
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if rd_data = '0' then
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stall_out <= '1';
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else
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stall_out <= '0';
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dmem_addr <= rd_data;
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end if;
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end if;
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else
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dmem_addr <= ex_mem_register.alu;
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end if;
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end if;
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-- store in mem
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if ex_mem_register.aluop1(ALUOP1_ST_MEM_BIT) = '1' then
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if ex_mem_register.aluop1(ALUOP1_ST_MEM_BIT) = '1' then
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if ex_mem_register.alu = CONST_ADDRESS then
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--write to Uart
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if sc_uart.rf_full = '1' then
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--stall
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stall_out <= '1';
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else
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stall_out <= '0';
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address <= ex_mem_register.alu;
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wr_data <= ex_mem_register.reg;
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wr <= '1';
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end if;
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else
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dmem_addr <= ex_mem_register.alu;
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dmem_addr <= ex_mem_register.alu;
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dmem_data_out <= ex_mem_register.reg;
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dmem_data_out <= ex_mem_register.reg;
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dmem_wr_enable <= '1';
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dmem_wr_enable <= '1';
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end if;
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end if;
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end if;
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-- other values are pass through
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-- other values are pass through
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mem_wb_register_next.aluop1 <= ex_mem_register.aluop1;
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mem_wb_register_next.aluop1 <= ex_mem_register.aluop1;
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mem_wb_register_next.aluop2 <= ex_mem_register.aluop2;
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mem_wb_register_next.aluop2 <= ex_mem_register.aluop2;
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mem_wb_register_next.reg <= ex_mem_register.alu;
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mem_wb_register_next.reg <= ex_mem_register.alu;
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