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-- File: dmem.vhd
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-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
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-- Created: 2006-11-29
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-- Last updated: 2006-11-29
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-- Description:
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-- Entity for accessing data memory.
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use ieee.numeric_std.all;
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use WORK.RISE_PACK.all;
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use WORK.CONF_PACK.all;
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entity memctrl is
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port (
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clk : in std_logic;
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reset : in std_logic;
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wr_enable : in std_logic;
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addr : in MEM_ADDR_T;
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data_in : in MEM_DATA_T;
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data_out : out MEM_DATA_T;
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uart_txd : out std_logic;
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uart_rxd : in std_logic);
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end memctrl;
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architecture memctrl_rtl of memctrl is
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component dmem
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port (
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addr : in std_logic_vector(DMEM_ADDR_WIDTH-1 downto 0);
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clk : in std_logic;
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data_in : in MEM_DATA_T;
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data_out : out MEM_DATA_T;
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wr_enable : in std_logic);
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end component;
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component sc_uart is
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generic (ADDR_BITS : integer;
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CLK_FREQ : integer;
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BAUD_RATE : integer;
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TXF_DEPTH : integer;
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TXF_THRES : integer;
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RXF_DEPTH : integer;
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RXF_THRES : integer);
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port (CLK : in std_logic;
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RESET : in std_logic;
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ADDRESS : in std_logic_vector(addr_bits-1 downto 0);
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WR_DATA : in std_logic_vector(15 downto 0);
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RD, WR : in std_logic;
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RD_DATA : out std_logic_vector(15 downto 0);
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RDY_CNT : out unsigned(1 downto 0);
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TXD : out std_logic;
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RXD : in std_logic;
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NCTS : in std_logic;
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NRTS : out std_logic);
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end component;
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signal uart_address : std_logic_vector(1 downto 0);
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signal uart_wr_data :std_logic_vector(15 downto 0);
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signal uart_rd : std_logic;
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signal uart_wr : std_logic;
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signal uart_rd_data : std_logic_vector(15 downto 0);
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signal uart_txd_sig : std_logic;
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signal uart_rxd_sig : std_logic;
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signal mem_addr : std_logic_vector (11 downto 0);
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signal mem_data_in :MEM_DATA_T;
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signal mem_data_out :MEM_DATA_T;
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signal mem_wr_enable: std_logic;
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signal last_address_int : MEM_ADDR_T;
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signal last_address_next : MEM_ADDR_T;
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signal rdy_cnt_sig : IEEE.NUMERIC_STD.unsigned(1 downto 0);
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begin -- dmem_rtl
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-- Uart modul einbinden
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UART : sc_uart generic map (
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ADDR_BITS => 2,
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CLK_FREQ => CLK_FREQ,
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BAUD_RATE => 115200,
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TXF_DEPTH => 2,
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TXF_THRES => 1,
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RXF_DEPTH => 2,
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RXF_THRES => 1
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)
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port map(
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CLK => clk,
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RESET => reset,
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ADDRESS => uart_address(1 downto 0),
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WR_DATA => uart_wr_data,
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RD => uart_rd,
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WR => uart_wr,
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RD_DATA => uart_rd_data,
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RDY_CNT => rdy_cnt_sig,
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TXD => uart_txd_sig,
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RXD => uart_rxd_sig,
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NCTS => '0',
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NRTS => open
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);
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DATA_MEM : dmem
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port map (
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addr => mem_addr,
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clk => clk,
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din => mem_data_in,
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dout => mem_data_out,
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sinit => reset,
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we => mem_wr_enable);
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uart_txd <= uart_txd_sig;
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uart_rxd_sig <= uart_rxd;
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store_address: process (clk, reset)
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begin -- process data_out
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if reset='0' then
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last_address_int <= (others => '0');
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elsif clk'event and clk='1' then
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last_address_int <= last_address_next;
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end if;
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end process store_address;
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process (last_address_int, mem_data_out, uart_rd_data)
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begin
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if last_address_int = CONST_UART_STATUS_ADDRESS
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or last_address_int = CONST_UART_DATA_ADDRESS then
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data_out <= uart_rd_data;
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else
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data_out <= mem_data_out;
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end if;
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end process;
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process (wr_enable, addr, data_in, uart_rd_data, mem_data_out)
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begin
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mem_addr <= (others => '0');
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mem_data_in <= (others => '0');
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mem_wr_enable <= '0';
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uart_address <= (others => '0');
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uart_wr <= '0';
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uart_wr_data <= (others => '0');
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uart_rd <= '0';
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last_address_next <= addr;
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if addr = CONST_UART_STATUS_ADDRESS
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or addr = CONST_UART_DATA_ADDRESS then
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-- accessing UART
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uart_address <= addr (1 downto 0);
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if wr_enable = '1' then
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uart_wr <= '1';
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uart_wr_data <= data_in;
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else
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uart_rd <= '1';
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end if;
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else
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-- accessing data memory
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mem_addr <= addr(11 downto 0);
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mem_data_in <= data_in;
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mem_wr_enable <= wr_enable;
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end if;
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end process;
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end memctrl_rtl;
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No newline at end of file
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No newline at end of file
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