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-- File: register_file.vhd
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-- File: register_file.vhd
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-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
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-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
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-- Created: 2006-11-29
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-- Created: 2006-11-29
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-- Last updated: 2006-11-29
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-- Last updated: 2006-11-29
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Line 40... |
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end register_file;
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end register_file;
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architecture register_file_rtl of register_file is
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architecture register_file_rtl of register_file is
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signal rx_read_next : REGISTER_T;
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signal ry_read_next : REGISTER_T;
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signal rz_read_next : REGISTER_T;
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signal sr_read_next : SR_REGISTER_T;
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signal pc_read_next : PC_REGISTER_T;
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signal dreg_addr_tmp : REGISTER_ADDR_T;
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signal dreg_write_tmp : REGISTER_T;
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signal sr_write_tmp : SR_REGISTER_T;
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signal lr_write_tmp : PC_REGISTER_T;
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signal pc_write_tmp : PC_REGISTER_T;
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signal regx_0, regx_1, regx_2, regx_3, regx_4 : REGISTER_T;
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signal regx_5, regx_6, regx_7, regx_8, regx_9 : REGISTER_T;
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signal regx_10, regx_11, regx_12, regx_13, regx_14, regx_15 : REGISTER_T;
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signal regy_0, regy_1, regy_2, regy_3, regy_4 : REGISTER_T;
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signal regy_5, regy_6, regy_7, regy_8, regy_9 : REGISTER_T;
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signal regy_10, regy_11, regy_12, regy_13, regy_14, regy_15 : REGISTER_T;
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signal regz_0, regz_1, regz_2, regz_3, regz_4 : REGISTER_T;
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signal regz_5, regz_6, regz_7, regz_8, regz_9 : REGISTER_T;
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signal regz_10, regz_11, regz_12, regz_13, regz_14, regz_15 : REGISTER_T;
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begin -- register_file_rtl
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begin -- register_file_rtl
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SYNC: process(clk, reset)
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begin
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if reset = '0' then
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rx_read <= (others => '0');
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ry_read <= (others => '0');
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rz_read <= (others => '0');
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sr_read <= (others => '0');
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pc_read <=( others => '0');
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sr_write_tmp <= (others => '0');
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lr_write_tmp <= (others => '0');
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pc_write_tmp <= (others => '0');
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dreg_addr_tmp <= (others => '0');
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dreg_write_tmp <= (others => '0');
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elsif clk'event and clk = '1' then
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rx_read <= rx_read_next;
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ry_read <= ry_read_next;
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rz_read <= rz_read_next;
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sr_read <= sr_read_next;
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pc_read <= pc_read_next;
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sr_write_tmp <= sr_write;
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lr_write_tmp <= lr_write;
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pc_write_tmp <= pc_write;
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dreg_addr_tmp <= dreg_addr;
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dreg_write_tmp <= dreg_write;
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end if;
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end process SYNC;
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WRITE: process(clk, reset)
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begin
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if reset = '0' then
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sr_read_next <= (others => '0');
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pc_read_next <= (others => '0');
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regx_0 <= (others => '0');
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regx_1 <= (others => '0');
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regx_2 <= (others => '0');
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regx_3 <= (others => '0');
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regx_4 <= (others => '0');
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regx_5 <= (others => '0');
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regx_6 <= (others => '0');
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regx_7 <= (others => '0');
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regx_8 <= (others => '0');
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regx_9 <= (others => '0');
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regx_10 <= (others => '0');
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regx_11 <= (others => '0');
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regx_12 <= (others => '0');
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regx_13 <= (others => '0');
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regx_14 <= (others => '0');
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regx_15 <= (others => '0');
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regy_0 <= (others => '0');
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regy_1 <= (others => '0');
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regy_2 <= (others => '0');
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regy_3 <= (others => '0');
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regy_4 <= (others => '0');
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regy_5 <= (others => '0');
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regy_6 <= (others => '0');
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regy_7 <= (others => '0');
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regy_8 <= (others => '0');
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regy_9 <= (others => '0');
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regy_10 <= (others => '0');
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regy_11 <= (others => '0');
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regy_12 <= (others => '0');
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regy_13 <= (others => '0');
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regy_14 <= (others => '0');
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regy_15 <= (others => '0');
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regz_0 <= (others => '0');
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regz_1 <= (others => '0');
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regz_2 <= (others => '0');
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regz_3 <= (others => '0');
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regz_4 <= (others => '0');
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regz_5 <= (others => '0');
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regz_6 <= (others => '0');
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regz_7 <= (others => '0');
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regz_8 <= (others => '0');
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regz_9 <= (others => '0');
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regz_10 <= (others => '0');
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regz_11 <= (others => '0');
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regz_12 <= (others => '0');
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regz_13 <= (others => '0');
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regz_14 <= (others => '0');
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regz_15 <= (others => '0');
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elsif clk'event and clk = '0' then
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sr_read_next <= sr_write_tmp;
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--lr_write_next <= lr_write_tmp;
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pc_read_next <= pc_write_tmp;
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if dreg_addr_tmp = "0000" then
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regx_0 <= dreg_write_tmp;
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regy_0 <= dreg_write_tmp;
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regz_0 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "0001" then
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regx_1 <= dreg_write_tmp;
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regy_1 <= dreg_write_tmp;
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regz_1 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "0010" then
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regx_2 <= dreg_write_tmp;
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regy_2 <= dreg_write_tmp;
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regz_2 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "0011" then
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regx_3 <= dreg_write_tmp;
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regy_3 <= dreg_write_tmp;
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regz_3 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "0100" then
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regx_4 <= dreg_write_tmp;
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regy_4 <= dreg_write_tmp;
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regz_4 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "0101" then
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regx_5 <= dreg_write_tmp;
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regy_5 <= dreg_write_tmp;
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regz_5 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "0110" then
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regx_6 <= dreg_write_tmp;
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regy_6 <= dreg_write_tmp;
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regz_6 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "0111" then
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regx_7 <= dreg_write_tmp;
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regy_7 <= dreg_write_tmp;
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regz_7 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "1000" then
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regx_8 <= dreg_write_tmp;
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regy_8 <= dreg_write_tmp;
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regz_8 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "1001" then
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regx_9 <= dreg_write_tmp;
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regy_9 <= dreg_write_tmp;
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regz_9 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "1010" then
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regx_10 <= dreg_write_tmp;
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regy_10 <= dreg_write_tmp;
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regz_10 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "1011" then
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regx_11 <= dreg_write_tmp;
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regy_11 <= dreg_write_tmp;
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regz_11 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "1100" then
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regx_12 <= dreg_write_tmp;
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regy_12 <= dreg_write_tmp;
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regz_12 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "1101" then
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regx_13 <= dreg_write_tmp;
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regy_13 <= dreg_write_tmp;
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regz_13 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "1110" then
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regx_14 <= dreg_write_tmp;
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regy_14 <= dreg_write_tmp;
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regz_14 <= dreg_write_tmp;
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elsif dreg_addr_tmp = "1111" then
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regx_15 <= dreg_write_tmp;
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regy_15 <= dreg_write_tmp;
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regz_15 <= dreg_write_tmp;
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end if;
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end if;
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end process WRITE;
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RX_READ_PROC: process(reset, rx_addr,
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regx_0, regx_1, regx_2, regx_3, regx_4, regx_5, regx_6, regx_7,
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regx_8, regx_9, regx_10, regx_11, regx_12, regx_13, regx_14, regx_15)
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begin
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if reset = '0' then
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rx_read_next <= (others => '0');
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else
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CASE rx_addr IS
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WHEN "0000" => rx_read_next <= regx_0;
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WHEN "0001" => rx_read_next <= regx_1;
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WHEN "0010" => rx_read_next <= regx_2;
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WHEN "0011" => rx_read_next <= regx_3;
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WHEN "0100" => rx_read_next <= regx_4;
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WHEN "0101" => rx_read_next <= regx_5;
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WHEN "0110" => rx_read_next <= regx_6;
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WHEN "0111" => rx_read_next <= regx_7;
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WHEN "1000" => rx_read_next <= regx_8;
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WHEN "1001" => rx_read_next <= regx_9;
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WHEN "1010" => rx_read_next <= regx_10;
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WHEN "1011" => rx_read_next <= regx_11;
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WHEN "1100" => rx_read_next <= regx_12;
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WHEN "1101" => rx_read_next <= regx_13;
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WHEN "1110" => rx_read_next <= regx_14;
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WHEN "1111" => rx_read_next <= regx_15;
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WHEN OTHERS => rx_read_next <= "XXXXXXXXXXXXXXXX";
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END CASE;
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end if;
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end process RX_READ_PROC;
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RY_READ_PROC: process(reset, ry_addr,
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regy_0, regy_1, regy_2, regy_3, regy_4, regy_5, regy_6, regy_7,
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regy_8, regy_9, regy_10, regy_11, regy_12, regy_13, regy_14, regy_15)
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begin
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if reset = '0' then
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ry_read_next <= (others => '0');
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else
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CASE ry_addr IS
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WHEN "0000" => ry_read_next <= regy_0;
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WHEN "0001" => ry_read_next <= regy_1;
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WHEN "0010" => ry_read_next <= regy_2;
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WHEN "0011" => ry_read_next <= regy_3;
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WHEN "0100" => ry_read_next <= regy_4;
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WHEN "0101" => ry_read_next <= regy_5;
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WHEN "0110" => ry_read_next <= regy_6;
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WHEN "0111" => ry_read_next <= regy_7;
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WHEN "1000" => ry_read_next <= regy_8;
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WHEN "1001" => ry_read_next <= regy_9;
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WHEN "1010" => ry_read_next <= regy_10;
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WHEN "1011" => ry_read_next <= regy_11;
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WHEN "1100" => ry_read_next <= regy_12;
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WHEN "1101" => ry_read_next <= regy_13;
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WHEN "1110" => ry_read_next <= regy_14;
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WHEN "1111" => ry_read_next <= regy_15;
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WHEN OTHERS => ry_read_next <= "XXXXXXXXXXXXXXXX";
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END CASE;
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end if;
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end process RY_READ_PROC;
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RZ_READ_PROC: process(reset, rz_addr,
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regz_0, regz_1, regz_2, regz_3, regz_4, regz_5, regz_6, regz_7,
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regz_8, regz_9, regz_10, regz_11, regz_12, regz_13, regz_14, regz_15)
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begin
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if reset = '0' then
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rz_read_next <= (others => '0');
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else
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CASE rz_addr IS
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WHEN "0000" => rz_read_next <= regz_0;
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WHEN "0001" => rz_read_next <= regz_1;
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WHEN "0010" => rz_read_next <= regz_2;
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WHEN "0011" => rz_read_next <= regz_3;
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WHEN "0100" => rz_read_next <= regz_4;
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WHEN "0101" => rz_read_next <= regz_5;
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WHEN "0110" => rz_read_next <= regz_6;
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WHEN "0111" => rz_read_next <= regz_7;
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WHEN "1000" => rz_read_next <= regz_8;
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WHEN "1001" => rz_read_next <= regz_9;
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WHEN "1010" => rz_read_next <= regz_10;
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WHEN "1011" => rz_read_next <= regz_11;
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WHEN "1100" => rz_read_next <= regz_12;
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WHEN "1101" => rz_read_next <= regz_13;
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WHEN "1110" => rz_read_next <= regz_14;
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WHEN "1111" => rz_read_next <= regz_15;
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WHEN OTHERS => rz_read_next <= "XXXXXXXXXXXXXXXX";
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END CASE;
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end if;
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end process RZ_READ_PROC;
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end register_file_rtl;
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end register_file_rtl;
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No newline at end of file
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No newline at end of file
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No newline at end of file
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No newline at end of file
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