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[/] [rise/] [trunk/] [vhdl/] [rise.vhd] - Diff between revs 94 and 124

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Rev 94 Rev 124
Line 78... Line 78...
  -- imem signals
  -- imem signals
  signal data_in_imem_sig          : MEM_DATA_T;  -- unused at the moment
  signal data_in_imem_sig          : MEM_DATA_T;  -- unused at the moment
  signal wr_enable_imem_sig        : std_logic;   -- unused at the moment
  signal wr_enable_imem_sig        : std_logic;   -- unused at the moment
  -- dmem signals
  -- dmem signals
  signal wr_enable_dmem_sig        : std_logic;
  signal wr_enable_dmem_sig        : std_logic;
 
  signal dmem_rxd_sig                     : std_logic;
 
  signal dmem_txd_sig                     : std_logic;
  -- rlu signals
  -- rlu signals
  signal clear_lock0_sig      : std_logic := '0';
  signal clear_lock0_sig      : std_logic := '0';
  signal clear_lock_addr0_sig : REGISTER_ADDR_T;
  signal clear_lock_addr0_sig : REGISTER_ADDR_T;
 
 
  signal clear_lock1_sig      : std_logic := '0';
  signal clear_lock1_sig      : std_logic := '0';
Line 241... Line 243...
      clk            : in std_logic;
      clk            : in std_logic;
      reset          : in std_logic;
      reset          : in std_logic;
      wr_enable      : in std_logic;
      wr_enable      : in std_logic;
      addr           : in MEM_ADDR_T;
      addr           : in MEM_ADDR_T;
      data_in        : in MEM_DATA_T;
      data_in        : in MEM_DATA_T;
      data_out       : out MEM_DATA_T);
      data_out       : out MEM_DATA_T;
 
                uart_txd                : out std_logic;
 
                uart_rxd                : in std_logic);
  end component;
  end component;
 
 
  component rlu
  component rlu
    port (
    port (
      clk   : in std_logic;
      clk   : in std_logic;
Line 412... Line 416...
      clk            => clk,
      clk            => clk,
      reset          => reset,
      reset          => reset,
      wr_enable      => wr_enable_dmem_sig,
      wr_enable      => wr_enable_dmem_sig,
      addr           => dmem_addr_sig,
      addr           => dmem_addr_sig,
      data_in        => dmem_data_out_sig,
      data_in        => dmem_data_out_sig,
      data_out       => dmem_data_in_sig);
      data_out       => dmem_data_in_sig,
 
                uart_txd                => dmem_txd_sig,
 
                uart_rxd                => dmem_rxd_sig);
 
 
  rlu_unit : rlu port map(
  rlu_unit : rlu port map(
    clk                 => clk,
    clk                 => clk,
    reset               => reset,
    reset               => reset,
    clear_locks         => clear_locks_sig,
    clear_locks         => clear_locks_sig,
Line 448... Line 454...
  branch_target_sig     <= ex_mem_register_sig.alu;
  branch_target_sig     <= ex_mem_register_sig.alu;
 
 
  data_in_imem_sig      <= (others => '-');  -- unused at the moment
  data_in_imem_sig      <= (others => '-');  -- unused at the moment
  wr_enable_imem_sig    <= '-';  -- unused at the moment
  wr_enable_imem_sig    <= '-';  -- unused at the moment
 
 
 
  --  ports of top level entity
 
  tx                                    <= dmem_txd_sig;
 
  dmem_rxd_sig          <= rx;
 
 
end rise_rtl;
end rise_rtl;
 
 
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