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[/] [rise/] [trunk/] [vhdl/] [rise.vhd] - Diff between revs 2 and 16

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Rev 2 Rev 16
Line 46... Line 46... 
  signal rx_sig                    : REGISTER_T;
 
  signal rx_sig                    : REGISTER_T;
 
  signal ry_sig                    : REGISTER_T;
 
  signal ry_sig                    : REGISTER_T;
 
  signal rz_sig                    : REGISTER_T;
 
  signal rz_sig                    : REGISTER_T;
 
  signal sr_id_sig                 : SR_REGISTER_T;
 
  signal sr_id_sig                 : SR_REGISTER_T;
 
  signal lock_register_sig         : LOCK_REGISTER_T;
 
  signal lock_register_sig         : LOCK_REGISTER_T;
 
  signal set_reg_lock_sig          : std_logic;
 
  signal set_reg_lock0_sig         : std_logic;
 
  signal lock_reg_addr_sig         : REGISTER_ADDR_T;
 
  signal lock_reg_addr0_sig        : REGISTER_ADDR_T;
 
 
 
  signal set_reg_lock1_sig         : std_logic;
 
 
 
  signal lock_reg_addr1_sig        : REGISTER_ADDR_T;
 
  signal stall_in_id_sig           : std_logic;
 
  signal stall_in_id_sig           : std_logic;
 
  signal stall_out_id_sig          : std_logic;
 
  signal stall_out_id_sig          : std_logic;
 
  signal clear_in_id_sig           : std_logic;
 
  signal clear_in_id_sig           : std_logic;
 
  -- ex_stage signals
 
  -- ex_stage signals
 
  signal ex_mem_register_sig       :  EX_MEM_REGISTER_T;
 
  signal ex_mem_register_sig       :  EX_MEM_REGISTER_T;
Line 70... Line 72... 
  signal dreg_addr_sig             : REGISTER_ADDR_T;
 
  signal dreg_addr_sig             : REGISTER_ADDR_T;
 
  signal dreg_sig                  : REGISTER_T;
 
  signal dreg_sig                  : REGISTER_T;
 
  signal lr_sig                    : PC_REGISTER_T;
 
  signal lr_sig                    : PC_REGISTER_T;
 
  signal sr_wb_sig                 : SR_REGISTER_T;
 
  signal sr_wb_sig                 : SR_REGISTER_T;
 
  signal clear_out_wb_sig          : std_logic;
 
  signal clear_out_wb_sig          : std_logic;
 
  signal clear_reg_lock_sig        : std_logic;
 
  signal clear_reg_lock0_sig       : std_logic;
 
 
 
  signal clear_reg_lock1_sig       : std_logic;
 
  -- imem signals
 
  -- imem signals
 
  signal data_in_imem_sig          : MEM_DATA_T;  -- unused at the moment
 
  signal data_in_imem_sig          : MEM_DATA_T;  -- unused at the moment
 
 
 
 
 
  component if_stage
 
  component if_stage
 
    port (
 
    port (
Line 111... Line 114... 
      ry             : in REGISTER_T;
 
      ry             : in REGISTER_T;
 
      rz             : in REGISTER_T;
 
      rz             : in REGISTER_T;
 
      sr             : in SR_REGISTER_T;
 
      sr             : in SR_REGISTER_T;
 
 
 
 
 
      lock_register  : in LOCK_REGISTER_T;
 
      lock_register  : in LOCK_REGISTER_T;
 
      set_reg_lock   : out std_logic;
 
      set_reg_lock0  : out std_logic;
 
      lock_reg_addr  : out REGISTER_ADDR_T;
 
      lock_reg_addr0 : out REGISTER_ADDR_T;
 
 
 
      set_reg_lock1  : out std_logic;
 
 
 
      lock_reg_addr1 : out REGISTER_ADDR_T;
 
 
 
 
 
      stall_in       : in std_logic;
 
      stall_in       : in std_logic;
 
      stall_out      : out std_logic;
 
      stall_out      : out std_logic;
 
      clear_in       : in std_logic);
 
      clear_in       : in std_logic);
 
  end component;
 
  end component;
Line 217... Line 222... 
      clk                 : in std_logic;
 
      clk                 : in std_logic;
 
      reset               : in std_logic;
 
      reset               : in std_logic;
 
 
 
 
 
      lock_register       : out LOCK_REGISTER_T;
 
      lock_register       : out LOCK_REGISTER_T;
 
 
 
 
 
      clear_reg_lock      : in std_logic;
 
      clear_reg_lock0     : in std_logic;
 
      set_reg_lock        : in std_logic;
 
      set_reg_lock0       : in std_logic;
 
      reg_addr            : in REGISTER_ADDR_T);
 
      reg_addr0           : in REGISTER_ADDR_T;
 
 
 
 
 
 
 
      clear_reg_lock1     : in std_logic;
 
 
 
      set_reg_lock1       : in std_logic;
 
 
 
      reg_addr1           : in REGISTER_ADDR_T );
 
  end component;
 
  end component;
 
 
 
 
 
begin  -- rise_rtl
 
begin  -- rise_rtl
 
 
 
 
 
  if_stage_unit : if_stage
 
  if_stage_unit : if_stage
Line 260... Line 269... 
      ry             => ry_sig,
 
      ry             => ry_sig,
 
      rz             => rz_sig,
 
      rz             => rz_sig,
 
      sr             => sr_id_sig,
 
      sr             => sr_id_sig,
 
 
 
 
 
      lock_register  => lock_register_sig,
 
      lock_register  => lock_register_sig,
 
      set_reg_lock   => set_reg_lock_sig,
 
      set_reg_lock0  => set_reg_lock0_sig,
 
      lock_reg_addr  => lock_reg_addr_sig,
 
      lock_reg_addr0 => lock_reg_addr0_sig,
 
 
 
      set_reg_lock1  => set_reg_lock1_sig,
 
 
 
      lock_reg_addr1 => lock_reg_addr1_sig,
 
 
 
 
 
      stall_in       => stall_in_id_sig,
 
      stall_in       => stall_in_id_sig,
 
      stall_out      => stall_out_id_sig,
 
      stall_out      => stall_out_id_sig,
 
      clear_in       => clear_in_id_sig);
 
      clear_in       => clear_in_id_sig);
 
 
 
 
Line 311... Line 322... 
      lr                  => lr_sig,
 
      lr                  => lr_sig,
 
      sr                  => sr_wb_sig,
 
      sr                  => sr_wb_sig,
 
 
 
 
 
      clear_out           => clear_out_wb_sig,
 
      clear_out           => clear_out_wb_sig,
 
 
 
 
 
      clear_reg_lock      => clear_reg_lock_sig);
 
      clear_reg_lock      => clear_reg_lock0_sig);
 
 
 
 
 
  register_file_unit : register_file
 
  register_file_unit : register_file
 
    port map (
 
    port map (
 
      clk            => clk,
 
      clk            => clk,
 
      reset          => reset,
 
      reset          => reset,
Line 359... Line 370... 
      clk                 => clk,
 
      clk                 => clk,
 
      reset               => reset,
 
      reset               => reset,
 
 
 
 
 
      lock_register       => lock_register_sig,
 
      lock_register       => lock_register_sig,
 
 
 
 
 
      clear_reg_lock      => clear_reg_lock_sig,
 
      clear_reg_lock0     => clear_reg_lock0_sig,
 
      set_reg_lock        => set_reg_lock_sig,
 
      set_reg_lock0       => set_reg_lock0_sig,
 
      reg_addr            => lock_reg_addr_sig);
 
      reg_addr0           => lock_reg_addr0_sig,
 
 
 
 
 
 
 
      clear_reg_lock1     => clear_reg_lock1_sig,
 
 
 
      set_reg_lock1       => set_reg_lock1_sig,
 
 
 
      reg_addr1           => lock_reg_addr1_sig
 
 
 
      );
 
 
 
 
 
  clear_in_if_sig       <= clear_out_ex_sig or clear_out_mem_sig or clear_out_wb_sig;
 
  clear_in_if_sig       <= clear_out_ex_sig or clear_out_mem_sig or clear_out_wb_sig;
 
  clear_in_id_sig       <= clear_in_if_sig;
 
  clear_in_id_sig       <= clear_in_if_sig;
 
  clear_in_ex_sig       <= clear_out_mem_sig or clear_out_wb_sig;
 
  clear_in_ex_sig       <= clear_out_mem_sig or clear_out_wb_sig;
 
  clear_in_mem_sig      <= clear_out_wb_sig;
 
  clear_in_mem_sig      <= clear_out_wb_sig;

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