| Line 69... |
Line 69... |
signal clear_in_mem_sig : std_logic;
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signal clear_in_mem_sig : std_logic;
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signal clear_out_mem_sig : std_logic;
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signal clear_out_mem_sig : std_logic;
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-- wb_stage signals
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-- wb_stage signals
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signal dreg_addr_sig : REGISTER_ADDR_T;
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signal dreg_addr_sig : REGISTER_ADDR_T;
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signal dreg_sig : REGISTER_T;
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signal dreg_sig : REGISTER_T;
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signal dreg_enable_sig : std_logic;
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signal lr_sig : PC_REGISTER_T;
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signal lr_sig : PC_REGISTER_T;
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signal lr_enable_sig : std_logic;
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signal sr_wb_sig : SR_REGISTER_T;
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signal sr_wb_sig : SR_REGISTER_T;
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signal sr_enable_sig : std_logic;
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signal clear_out_wb_sig : std_logic;
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signal clear_out_wb_sig : std_logic;
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signal clear_reg_lock0_sig : std_logic;
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signal clear_reg_lock0_sig : std_logic;
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signal clear_reg_lock1_sig : std_logic;
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signal clear_reg_lock1_sig : std_logic;
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-- imem signals
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-- imem signals
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signal data_in_imem_sig : MEM_DATA_T; -- unused at the moment
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signal data_in_imem_sig : MEM_DATA_T; -- unused at the moment
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| Line 164... |
Line 167... |
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mem_wb_register : in MEM_WB_REGISTER_T;
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mem_wb_register : in MEM_WB_REGISTER_T;
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dreg_addr : out REGISTER_ADDR_T;
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dreg_addr : out REGISTER_ADDR_T;
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dreg : out REGISTER_T;
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dreg : out REGISTER_T;
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dreg_enable : out std_logic;
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lr : out PC_REGISTER_T;
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lr : out PC_REGISTER_T;
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lr_enable : in std_logic;
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sr : out SR_REGISTER_T;
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sr : out SR_REGISTER_T;
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sr_enable : out std_logic;
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clear_out : out std_logic;
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clear_out : out std_logic;
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clear_reg_lock : out std_logic);
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clear_reg_lock : out std_logic);
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end component;
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end component;
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| Line 181... |
Line 188... |
reset : in std_logic;
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reset : in std_logic;
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rx_addr : in REGISTER_ADDR_T;
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rx_addr : in REGISTER_ADDR_T;
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ry_addr : in REGISTER_ADDR_T;
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ry_addr : in REGISTER_ADDR_T;
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rz_addr : in REGISTER_ADDR_T;
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rz_addr : in REGISTER_ADDR_T;
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dreg_addr : in REGISTER_ADDR_T;
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dreg_write : in REGISTER_T;
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rx_read : out REGISTER_T;
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rx_read : out REGISTER_T;
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ry_read : out REGISTER_T;
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ry_read : out REGISTER_T;
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rz_read : out REGISTER_T;
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rz_read : out REGISTER_T;
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dreg_addr : in REGISTER_ADDR_T;
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dreg_write : in REGISTER_T;
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dreg_enable : in std_logic;
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sr_read : out SR_REGISTER_T;
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sr_write : in SR_REGISTER_T;
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sr_write : in SR_REGISTER_T;
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sr_enable : in std_logic;
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lr_write : in PC_REGISTER_T;
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lr_write : in PC_REGISTER_T;
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lr_enable : in std_logic;
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pc_write : in PC_REGISTER_T;
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pc_write : in PC_REGISTER_T;
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sr_read : out SR_REGISTER_T;
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pc_read : out PC_REGISTER_T);
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pc_read : out PC_REGISTER_T);
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end component;
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end component;
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component imem
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component imem
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port (
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port (
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| Line 316... |
Line 329... |
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mem_wb_register => mem_wb_register_sig,
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mem_wb_register => mem_wb_register_sig,
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dreg_addr => dreg_addr_sig,
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dreg_addr => dreg_addr_sig,
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dreg => dreg_sig,
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dreg => dreg_sig,
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dreg_enable => dreg_enable_sig,
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lr => lr_sig,
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lr => lr_sig,
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lr_enable => lr_enable_sig,
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sr => sr_wb_sig,
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sr => sr_wb_sig,
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sr_enable => sr_enable_sig,
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clear_out => clear_out_wb_sig,
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clear_out => clear_out_wb_sig,
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clear_reg_lock => clear_reg_lock0_sig);
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clear_reg_lock => clear_reg_lock0_sig);
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| Line 332... |
Line 349... |
reset => reset,
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reset => reset,
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rx_addr => rx_addr_sig,
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rx_addr => rx_addr_sig,
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ry_addr => ry_addr_sig,
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ry_addr => ry_addr_sig,
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rz_addr => rz_addr_sig,
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rz_addr => rz_addr_sig,
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dreg_addr => dreg_addr_sig,
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dreg_write => dreg_sig,
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rx_read => rx_sig,
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rx_read => rx_sig,
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ry_read => ry_sig,
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ry_read => ry_sig,
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rz_read => rz_sig,
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rz_read => rz_sig,
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dreg_addr => dreg_addr_sig,
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dreg_write => dreg_sig,
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dreg_enable => dreg_enable_sig,
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sr_read => sr_id_sig,
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sr_write => sr_wb_sig,
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sr_write => sr_wb_sig,
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sr_enable => sr_enable_sig,
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lr_write => lr_sig,
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lr_write => lr_sig,
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lr_enable => lr_enable_sig,
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pc_write => pc_next_if_sig,
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pc_write => pc_next_if_sig,
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sr_read => sr_id_sig,
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pc_read => pc_if_sig);
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pc_read => pc_if_sig);
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imem_unit : imem
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imem_unit : imem
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port map (
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port map (
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clk => clk,
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clk => clk,
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