| Line 55... |
Line 55... |
-- ex_stage signals
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-- ex_stage signals
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signal ex_mem_register_sig : EX_MEM_REGISTER_T;
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signal ex_mem_register_sig : EX_MEM_REGISTER_T;
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signal stall_in_ex_sig : std_logic;
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signal stall_in_ex_sig : std_logic;
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signal clear_in_ex_sig : std_logic;
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signal clear_in_ex_sig : std_logic;
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signal clear_out_ex_sig : std_logic;
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signal clear_out_ex_sig : std_logic;
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signal clear_locks_sig : std_logic;
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-- mem_stage signals
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-- mem_stage signals
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signal mem_wb_register_sig : MEM_WB_REGISTER_T;
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signal mem_wb_register_sig : MEM_WB_REGISTER_T;
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signal dmem_addr_sig : MEM_ADDR_T;
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signal dmem_addr_sig : MEM_ADDR_T;
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signal dmem_data_in_sig : MEM_DATA_T;
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signal dmem_data_in_sig : MEM_DATA_T;
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signal dmem_data_out_sig : MEM_DATA_T;
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signal dmem_data_out_sig : MEM_DATA_T;
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| Line 148... |
Line 149... |
ex_mem_register : out EX_MEM_REGISTER_T;
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ex_mem_register : out EX_MEM_REGISTER_T;
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branch : out std_logic;
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branch : out std_logic;
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stall_in : in std_logic;
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stall_in : in std_logic;
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clear_in : in std_logic;
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clear_in : in std_logic;
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clear_out : out std_logic);
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clear_out : out std_logic;
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clear_locks : out std_logic);
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end component;
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end component;
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component mem_stage
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component mem_stage
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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| Line 246... |
Line 248... |
|
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component rlu
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component rlu
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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clear_locks : in std_logic;
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lock_register : out LOCK_REGISTER_T;
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lock_register : out LOCK_REGISTER_T;
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|
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set_lock0 : in std_logic;
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set_lock0 : in std_logic;
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set_lock_addr0 : in REGISTER_ADDR_T;
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set_lock_addr0 : in REGISTER_ADDR_T;
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| Line 322... |
Line 325... |
ex_mem_register => ex_mem_register_sig,
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ex_mem_register => ex_mem_register_sig,
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branch => branch_sig,
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branch => branch_sig,
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stall_in => stall_in_ex_sig,
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stall_in => stall_in_ex_sig,
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clear_in => clear_in_ex_sig,
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clear_in => clear_in_ex_sig,
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clear_out => clear_out_ex_sig);
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clear_out => clear_out_ex_sig,
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clear_locks => clear_locks_sig);
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mem_stage_unit : mem_stage
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mem_stage_unit : mem_stage
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port map (
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port map (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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| Line 413... |
Line 417... |
data_out => dmem_data_in_sig);
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data_out => dmem_data_in_sig);
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rlu_unit : rlu port map(
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rlu_unit : rlu port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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clear_locks => clear_locks_sig,
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lock_register => lock_register_sig,
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lock_register => lock_register_sig,
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set_lock0 => set_lock0_sig,
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set_lock0 => set_lock0_sig,
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set_lock_addr0 => set_lock_addr0_sig,
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set_lock_addr0 => set_lock_addr0_sig,
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