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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use work.RISE_PACK_SPECIFIC.all;
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package RISE_PACK is
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package RISE_PACK is
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constant ARCHITECTURE_WIDTH : integer := 16;
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constant ARCHITECTURE_WIDTH : integer := 16;
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constant REGISTER_COUNT : integer := 16;
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constant REGISTER_COUNT : integer := 16;
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constant PC_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant PC_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant IR_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant IR_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant SR_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant SR_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant OPCODE_WIDTH : integer := 5;
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constant COND_WIDTH : integer := 3;
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constant MEM_DATA_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant MEM_DATA_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant MEM_ADDR_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant MEM_ADDR_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant REGISTER_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant REGISTER_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant REGISTER_ADDR_WIDTH : integer := 4;
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constant REGISTER_ADDR_WIDTH : integer := 4;
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subtype MEM_ADDR_T is std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
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subtype MEM_ADDR_T is std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
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subtype LOCK_REGISTER_T is std_logic_vector(LOCK_WIDTH-1 downto 0);
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subtype LOCK_REGISTER_T is std_logic_vector(LOCK_WIDTH-1 downto 0);
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subtype IMMEDIATE_T is std_logic_vector(IMMEDIATE_WIDTH-1 downto 0);
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subtype IMMEDIATE_T is std_logic_vector(IMMEDIATE_WIDTH-1 downto 0);
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subtype OPCODE_T is std_logic_vector(OPCODE_WIDTH-1 downto 0);
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subtype COND_T is std_logic_vector(COND_WIDTH-1 downto 0);
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subtype ALUOP1_T is std_logic_vector(ALUOP1_WIDTH-1 downto 0);
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subtype ALUOP1_T is std_logic_vector(ALUOP1_WIDTH-1 downto 0);
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subtype ALUOP2_T is std_logic_vector(ALUOP2_WIDTH-1 downto 0);
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subtype ALUOP2_T is std_logic_vector(ALUOP2_WIDTH-1 downto 0);
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--
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--
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constant PC_ADDR : REGISTER_ADDR_T := CONV_STD_LOGIC_VECTOR(14, REGISTER_ADDR_WIDTH);
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constant PC_ADDR : REGISTER_ADDR_T := CONV_STD_LOGIC_VECTOR(14, REGISTER_ADDR_WIDTH);
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constant PC_RESET_VECTOR : MEM_ADDR_T := x"FFFE";
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constant PC_RESET_VECTOR : MEM_ADDR_T := x"FFFE";
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-- RISE OPCODES --
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-- load opcodes
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constant OPCODE_LD_IMM : OPCODE_T := "10000";
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constant OPCODE_LD_IMM_HB : OPCODE_T := "10010";
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constant OPCODE_LD_DISP : OPCODE_T := "10100";
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constant OPCODE_LD_DISP_MS : OPCODE_T := "11000";
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constant OPCODE_LD_REG : OPCODE_T := "00001";
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-- store opcodes
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constant OPCODE_ST_DISP : OPCODE_T := "11100";
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-- arithmethic opcodes
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constant OPCODE_ADD : OPCODE_T := "00010";
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constant OPCODE_ADD_IMM : OPCODE_T := "00011";
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constant OPCODE_SUB : OPCODE_T := "00100";
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constant OPCODE_SUB_IMM : OPCODE_T := "00101";
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constant OPCODE_NEG : OPCODE_T := "00110";
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constant OPCODE_ARS : OPCODE_T := "00111";
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constant OPCODE_ALS : OPCODE_T := "01000";
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-- logical opcodes
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constant OPCODE_AND : OPCODE_T := "01001";
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constant OPCODE_NOT : OPCODE_T := "01010";
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constant OPCODE_EOR : OPCODE_T := "01011";
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constant OPCODE_LS : OPCODE_T := "01100";
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constant OPCODE_RS : OPCODE_T := "01101";
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-- program control
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constant OPCODE_JMP : OPCODE_T := "01110";
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-- other
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constant OPCODE_TST : OPCODE_T := "01111";
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constant OPCODE_NOP : OPCODE_T := "00000";
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-- CONDITION CODES --
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constant COND_UNCONDITIONAL : COND_T := "000";
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constant COND_NOT_ZERO : COND_T := "001";
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constant COND_ZERO : COND_T := "010";
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constant COND_CARRY : COND_T := "011";
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constant COND_NEGATIVE : COND_T := "100";
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constant COND_OVERFLOW : COND_T := "101";
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constant COND_ZERO_NEGATIVE : COND_T := "110";
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-- STATUS REGISTER BITS --
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-- STATUS REGISTER BITS --
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constant SR_ZERO_BIT : integer := 0;
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constant SR_ZERO_BIT : integer := 0;
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constant SR_CARRY_BIT : integer := 1;
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constant SR_CARRY_BIT : integer := 1;
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constant SR_NEGATIVE_BIT : integer := 2;
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constant SR_NEGATIVE_BIT : integer := 2;
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