| Line 51... |
Line 51... |
signal reset : std_logic := '0';
|
signal reset : std_logic := '0';
|
signal if_id_register : IF_ID_REGISTER_T;
|
signal if_id_register : IF_ID_REGISTER_T;
|
|
|
signal stall_in : std_logic := '0';
|
signal stall_in : std_logic := '0';
|
signal clear_in : std_logic := '0';
|
signal clear_in : std_logic := '0';
|
signal rx : REGISTER_T := (others => '0');
|
signal rx : REGISTER_T;
|
signal ry : REGISTER_T := (others => '0');
|
signal ry : REGISTER_T;
|
signal rz : REGISTER_T := (others => '0');
|
signal rz : REGISTER_T;
|
signal sr : SR_REGISTER_T := (others => '0');
|
signal sr : SR_REGISTER_T;
|
signal lock_register : LOCK_REGISTER_T;
|
signal lock_register : LOCK_REGISTER_T;
|
--Outputs
|
--Outputs
|
signal id_ex_register : ID_EX_REGISTER_T;
|
signal id_ex_register : ID_EX_REGISTER_T;
|
signal rx_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
|
signal rx_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
|
signal ry_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
|
signal ry_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
|
signal rz_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
|
signal rz_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
|
signal set_reg_lock : std_logic;
|
signal set_reg_lock : std_logic;
|
signal lock_reg_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
|
signal lock_reg_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
|
signal stall_out : std_logic;
|
signal stall_out : std_logic;
|
|
|
|
constant TB_RX_ADDR_TEST_VALUE : REGISTER_ADDR_T := x"1";
|
|
constant TB_RX_TEST_VALUE : REGISTER_T := x"0001";
|
|
constant TB_RY_TEST_VALUE : REGISTER_T := x"0002";
|
|
constant TB_RZ_TEST_VALUE : REGISTER_T := x"0003";
|
|
constant TB_SR_TEST_VALUE : SR_REGISTER_T := x"A55A";
|
|
constant TB_PC_TEST_VALUE : SR_REGISTER_T := x"1234";
|
|
|
|
constant TB_CLOCK : time := 20 ns;
|
begin
|
begin
|
|
|
-- instantiate the Unit Under Test (UUT)
|
-- instantiate the Unit Under Test (UUT)
|
uut : id_stage port map(
|
uut : id_stage port map(
|
clk => clk,
|
clk => clk,
|
| Line 91... |
Line 99... |
);
|
);
|
|
|
cg : process
|
cg : process
|
begin
|
begin
|
clk <= '0';
|
clk <= '0';
|
wait for 10 ns;
|
wait for TB_CLOCK/2;
|
clk <= '1';
|
clk <= '1';
|
wait for 10 ns;
|
wait for TB_CLOCK/2;
|
end process;
|
end process;
|
|
|
tb : process
|
tb : process
|
begin
|
begin
|
reset <= '0';
|
reset <= '0';
|
wait for 100 ns;
|
wait for 100 ns;
|
reset <= '1';
|
reset <= '1';
|
|
|
-- stimulus
|
-- test case: basic functionallity
|
if_id_register.pc <= x"1234";
|
if_id_register.pc <= TB_PC_TEST_VALUE;
|
if_id_register.ir <= "100"& "0" & "0001" & x"55";
|
sr <= TB_SR_TEST_VALUE;
|
|
rx <= TB_RX_TEST_VALUE;
|
|
ry <= TB_RY_TEST_VALUE;
|
|
rz <= TB_RZ_TEST_VALUE;
|
|
|
|
wait for TB_CLOCK;
|
|
|
|
-- test case: OPCODE_LD_IMM
|
|
if_id_register.ir <= "100"& "0" & TB_RX_ADDR_TEST_VALUE & x"55";
|
|
wait for TB_CLOCK;
|
|
assert id_ex_register.opcode = OPCODE_LD_IMM;
|
|
assert id_ex_register.immediate = x"0055";
|
|
assert id_ex_register.cond = COND_UNCONDITIONAL;
|
|
assert rx_addr = TB_RX_ADDR_TEST_VALUE;
|
|
assert id_ex_register.rX_addr = TB_RX_ADDR_TEST_VALUE;
|
|
assert id_ex_register.rX = TB_RX_TEST_VALUE;
|
|
|
|
-- test case: OPCODE_LD_IMM_HB
|
|
if_id_register.ir <= "100"& "1" & TB_RX_ADDR_TEST_VALUE & x"55";
|
|
wait for TB_CLOCK;
|
|
assert id_ex_register.opcode = OPCODE_LD_IMM_HB;
|
|
assert id_ex_register.immediate = x"5500";
|
|
assert id_ex_register.cond = COND_UNCONDITIONAL;
|
|
assert rx_addr = TB_RX_ADDR_TEST_VALUE;
|
|
assert id_ex_register.rX_addr = TB_RX_ADDR_TEST_VALUE;
|
|
assert id_ex_register.rX = TB_RX_TEST_VALUE;
|
|
|
wait; -- will wait forever
|
wait; -- will wait forever
|
end process;
|
end process;
|
|
|
end;
|
end;
|
