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signal rz_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
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signal rz_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
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signal set_reg_lock : std_logic;
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signal set_reg_lock : std_logic;
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signal lock_reg_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
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signal lock_reg_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
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signal stall_out : std_logic;
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signal stall_out : std_logic;
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constant TB_RX_ADDR_TEST_VALUE : REGISTER_ADDR_T := x"1";
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constant TB_COND_TEST_VALUE : COND_T := COND_NONE;
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constant TB_RX_TEST_VALUE : REGISTER_T := x"0001";
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constant TB_RY_TEST_VALUE : REGISTER_T := x"0002";
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constant TB_R1_TEST_VALUE : REGISTER_T := x"0001";
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constant TB_RZ_TEST_VALUE : REGISTER_T := x"0003";
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constant TB_R2_TEST_VALUE : REGISTER_T := x"0002";
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constant TB_R3_TEST_VALUE : REGISTER_T := x"0003";
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constant TB_SR_TEST_VALUE : SR_REGISTER_T := x"A55A";
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constant TB_SR_TEST_VALUE : SR_REGISTER_T := x"A55A";
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constant TB_PC_TEST_VALUE : SR_REGISTER_T := x"1234";
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constant TB_PC_TEST_VALUE : SR_REGISTER_T := x"1234";
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constant TB_CLOCK : time := 20 ns;
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constant TB_CLOCK : time := 20 ns;
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begin
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begin
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wait for TB_CLOCK/2;
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wait for TB_CLOCK/2;
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clk <= '1';
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clk <= '1';
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wait for TB_CLOCK/2;
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wait for TB_CLOCK/2;
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end process;
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end process;
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regfile : process(rx_addr, ry_addr, rz_addr)
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begin
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case rx_addr is
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when x"1" => rx <= TB_R1_TEST_VALUE;
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when x"2" => rx <= TB_R2_TEST_VALUE;
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when x"3" => rx <= TB_R3_TEST_VALUE;
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when others => rz <= (others => 'X');
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end case;
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case ry_addr is
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when x"1" => ry <= TB_R1_TEST_VALUE;
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when x"2" => ry <= TB_R2_TEST_VALUE;
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when x"3" => ry <= TB_R3_TEST_VALUE;
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when others => rz <= (others => 'X');
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end case;
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case rz_addr is
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when x"1" => rz <= TB_R1_TEST_VALUE;
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when x"2" => rz <= TB_R2_TEST_VALUE;
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when x"3" => rz <= TB_R3_TEST_VALUE;
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when others => rz <= (others => 'X');
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end case;
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sr <= TB_SR_TEST_VALUE;
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end process;
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tb : process
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tb : process
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begin
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begin
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reset <= '0';
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reset <= '0';
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wait for 100 ns;
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wait for 100 ns;
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reset <= '1';
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reset <= '1';
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-- test case: basic functionallity
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-- test case: basic functionallity
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if_id_register.pc <= TB_PC_TEST_VALUE;
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if_id_register.pc <= TB_PC_TEST_VALUE;
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sr <= TB_SR_TEST_VALUE;
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rx <= TB_RX_TEST_VALUE;
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ry <= TB_RY_TEST_VALUE;
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rz <= TB_RZ_TEST_VALUE;
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wait for TB_CLOCK;
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wait for TB_CLOCK;
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-- test case: OPCODE_LD_IMM
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-- test case: OPCODE_LD_IMM
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if_id_register.ir <= "100"& "0" & TB_RX_ADDR_TEST_VALUE & x"55";
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if_id_register.ir <= "100"& "0" & x"1" & x"55";
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wait for TB_CLOCK;
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wait for TB_CLOCK;
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assert id_ex_register.opcode = OPCODE_LD_IMM;
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assert id_ex_register.opcode = OPCODE_LD_IMM;
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assert id_ex_register.immediate = x"0055";
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assert id_ex_register.immediate = x"0055";
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assert id_ex_register.cond = COND_UNCONDITIONAL;
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assert id_ex_register.cond = COND_UNCONDITIONAL;
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assert rx_addr = TB_RX_ADDR_TEST_VALUE;
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assert rx_addr = x"1";
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assert id_ex_register.rX_addr = TB_RX_ADDR_TEST_VALUE;
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assert id_ex_register.rX_addr = x"1";
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assert id_ex_register.rX = TB_RX_TEST_VALUE;
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assert id_ex_register.rX = TB_R1_TEST_VALUE;
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-- test case: OPCODE_LD_IMM_HB
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if_id_register.ir <= "100"& "1" & x"1" & x"55";
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wait for TB_CLOCK;
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assert id_ex_register.opcode = OPCODE_LD_IMM_HB;
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assert id_ex_register.immediate = x"5500";
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assert id_ex_register.cond = COND_UNCONDITIONAL;
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assert rx_addr = x"1";
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assert id_ex_register.rX_addr = x"1";
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assert id_ex_register.rX = TB_R1_TEST_VALUE;
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-- test case: OPCODE_LD_IMM_HB
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-- test case: OPCODE_LD_IMM_HB
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if_id_register.ir <= "100"& "1" & TB_RX_ADDR_TEST_VALUE & x"55";
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if_id_register.ir <= "100"& "1" & x"1" & x"55";
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wait for TB_CLOCK;
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wait for TB_CLOCK;
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assert id_ex_register.opcode = OPCODE_LD_IMM_HB;
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assert id_ex_register.opcode = OPCODE_LD_IMM_HB;
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assert id_ex_register.immediate = x"5500";
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assert id_ex_register.immediate = x"5500";
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assert id_ex_register.cond = COND_UNCONDITIONAL;
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assert id_ex_register.cond = COND_UNCONDITIONAL;
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assert rx_addr = TB_RX_ADDR_TEST_VALUE;
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assert rx_addr = x"1";
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assert id_ex_register.rX_addr = TB_RX_ADDR_TEST_VALUE;
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assert id_ex_register.rX_addr = x"1";
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assert id_ex_register.rX = TB_RX_TEST_VALUE;
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assert id_ex_register.rX = TB_R1_TEST_VALUE;
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-- test case: OPCODE_LD_DISP
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if_id_register.ir <= "101"& "000" & "11" & x"1" & x"2";
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wait for TB_CLOCK;
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assert id_ex_register.opcode = OPCODE_LD_DISP;
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assert id_ex_register.rX_addr = x"1";
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assert id_ex_register.rX = TB_R1_TEST_VALUE;
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assert id_ex_register.rY = TB_R2_TEST_VALUE;
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assert id_ex_register.rZ = TB_R3_TEST_VALUE;
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assert id_ex_register.cond = TB_COND_TEST_VALUE;
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assert rx_addr = x"1";
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assert ry_addr = x"2";
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assert rz_addr = x"3";
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-- test case: OPCODE_LD_DISP_MS
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if_id_register.ir <= "110" & "000" & "11" & x"1" & x"2";
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wait for TB_CLOCK;
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assert id_ex_register.opcode = OPCODE_LD_DISP_MS;
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assert id_ex_register.rX_addr = x"1";
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assert id_ex_register.rX = TB_R1_TEST_VALUE;
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assert id_ex_register.rY = TB_R2_TEST_VALUE;
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assert id_ex_register.rZ = TB_R3_TEST_VALUE;
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assert id_ex_register.cond = TB_COND_TEST_VALUE;
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assert rx_addr = x"1";
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assert ry_addr = x"2";
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assert rz_addr = x"3";
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-- test case: OPCODE_LD_REG
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if_id_register.ir <= "00001" & "001" & x"2" & x"1";
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wait for TB_CLOCK;
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assert id_ex_register.opcode = OPCODE_LD_REG;
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assert id_ex_register.rX_addr = x"2";
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assert id_ex_register.rX = TB_R2_TEST_VALUE;
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assert id_ex_register.rY = TB_R1_TEST_VALUE;
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assert id_ex_register.cond = COND_NOT_ZERO;
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assert rx_addr = x"2";
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assert ry_addr = x"1";
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wait; -- will wait forever
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wait; -- will wait forever
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end process;
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end process;
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end;
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end;
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