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[/] [rise/] [trunk/] [vhdl/] [tb_id_stage_unit.vhd] - Diff between revs 10 and 13

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Rev 10 Rev 13
Line 65... Line 65... 
  signal rz_addr        : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
 
  signal rz_addr        : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
 
  signal set_reg_lock   : std_logic;
 
  signal set_reg_lock   : std_logic;
 
  signal lock_reg_addr  : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
 
  signal lock_reg_addr  : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
 
  signal stall_out      : std_logic;
 
  signal stall_out      : std_logic;
 
 
 
 
 
  constant TB_RX_ADDR_TEST_VALUE : REGISTER_ADDR_T := x"1";
 
  constant TB_COND_TEST_VALUE : COND_T := COND_NONE;
 
  constant TB_RX_TEST_VALUE : REGISTER_T := x"0001";
 
 
 
  constant TB_RY_TEST_VALUE : REGISTER_T := x"0002";
 
  constant TB_R1_TEST_VALUE : REGISTER_T := x"0001";
 
  constant TB_RZ_TEST_VALUE : REGISTER_T := x"0003";
 
  constant TB_R2_TEST_VALUE : REGISTER_T := x"0002";
 
 
 
  constant TB_R3_TEST_VALUE : REGISTER_T := x"0003";
 
 
 
 
 
  constant TB_SR_TEST_VALUE : SR_REGISTER_T := x"A55A";
 
  constant TB_SR_TEST_VALUE : SR_REGISTER_T := x"A55A";
 
  constant TB_PC_TEST_VALUE : SR_REGISTER_T := x"1234";
 
  constant TB_PC_TEST_VALUE : SR_REGISTER_T := x"1234";
 
 
 
 
 
  constant TB_CLOCK : time := 20 ns;
 
  constant TB_CLOCK : time := 20 ns;
 
begin
 
begin
Line 104... Line 106... 
    wait for TB_CLOCK/2;
 
    wait for TB_CLOCK/2;
 
    clk <= '1';
 
    clk <= '1';
 
    wait for TB_CLOCK/2;
 
    wait for TB_CLOCK/2;
 
  end process;
 
  end process;
 
 
 
 
 
 
 
  regfile : process(rx_addr, ry_addr, rz_addr)
 
 
 
  begin
 
 
 
    case rx_addr is
 
 
 
      when x"1"   => rx <= TB_R1_TEST_VALUE;
 
 
 
      when x"2"   => rx <= TB_R2_TEST_VALUE;
 
 
 
      when x"3"   => rx <= TB_R3_TEST_VALUE;
 
 
 
      when others => rz <= (others => 'X');
 
 
 
    end case;
 
 
 
 
 
 
 
    case ry_addr is
 
 
 
      when x"1"   => ry <= TB_R1_TEST_VALUE;
 
 
 
      when x"2"   => ry <= TB_R2_TEST_VALUE;
 
 
 
      when x"3"   => ry <= TB_R3_TEST_VALUE;
 
 
 
      when others => rz <= (others => 'X');
 
 
 
    end case;
 
 
 
 
 
 
 
    case rz_addr is
 
 
 
      when x"1"   => rz <= TB_R1_TEST_VALUE;
 
 
 
      when x"2"   => rz <= TB_R2_TEST_VALUE;
 
 
 
      when x"3"   => rz <= TB_R3_TEST_VALUE;
 
 
 
      when others => rz <= (others => 'X');
 
 
 
    end case;
 
 
 
 
 
 
 
    sr <= TB_SR_TEST_VALUE;
 
 
 
 
 
 
 
  end process;
 
 
 
 
 
  tb : process
 
  tb : process
 
  begin
 
  begin
 
    reset <= '0';
 
    reset <= '0';
 
    wait for 100 ns;
 
    wait for 100 ns;
 
    reset <= '1';
 
    reset <= '1';
 
 
 
 
 
    -- test case: basic functionallity
 
    -- test case: basic functionallity
 
    if_id_register.pc <= TB_PC_TEST_VALUE;
 
    if_id_register.pc <= TB_PC_TEST_VALUE;
 
    sr <= TB_SR_TEST_VALUE;
 
 
 
    rx <= TB_RX_TEST_VALUE;
 
 
 
    ry <= TB_RY_TEST_VALUE;
 
 
 
    rz <= TB_RZ_TEST_VALUE;
 
 
 
 
 
 
 
    wait for TB_CLOCK;
 
    wait for TB_CLOCK;
 
 
 
 
 
    -- test case: OPCODE_LD_IMM 
    -- test case: OPCODE_LD_IMM 
    if_id_register.ir <= "100"& "0" & TB_RX_ADDR_TEST_VALUE & x"55";
 
    if_id_register.ir <= "100"& "0" & x"1" & x"55";
 
    wait for TB_CLOCK;
 
    wait for TB_CLOCK;
 
    assert id_ex_register.opcode = OPCODE_LD_IMM;
 
    assert id_ex_register.opcode = OPCODE_LD_IMM;
 
    assert id_ex_register.immediate = x"0055";
 
    assert id_ex_register.immediate = x"0055";
 
    assert id_ex_register.cond = COND_UNCONDITIONAL;
 
    assert id_ex_register.cond = COND_UNCONDITIONAL;
 
    assert rx_addr = TB_RX_ADDR_TEST_VALUE;
 
    assert rx_addr = x"1";
 
    assert id_ex_register.rX_addr = TB_RX_ADDR_TEST_VALUE;
 
    assert id_ex_register.rX_addr = x"1";
 
    assert id_ex_register.rX = TB_RX_TEST_VALUE;
 
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
 
 
 
 
 
 
 
    -- test case: OPCODE_LD_IMM_HB
 
 
 
    if_id_register.ir <= "100"& "1" & x"1" & x"55";
 
 
 
    wait for TB_CLOCK;
 
 
 
    assert id_ex_register.opcode = OPCODE_LD_IMM_HB;
 
 
 
    assert id_ex_register.immediate = x"5500";
 
 
 
    assert id_ex_register.cond = COND_UNCONDITIONAL;
 
 
 
    assert rx_addr = x"1";
 
 
 
    assert id_ex_register.rX_addr = x"1";
 
 
 
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
 
 
 
 
 
 
 
 
 
    -- test case: OPCODE_LD_IMM_HB
 
    -- test case: OPCODE_LD_IMM_HB
 
    if_id_register.ir <= "100"& "1" & TB_RX_ADDR_TEST_VALUE & x"55";
 
    if_id_register.ir <= "100"& "1" & x"1" & x"55";
 
    wait for TB_CLOCK;
 
    wait for TB_CLOCK;
 
    assert id_ex_register.opcode = OPCODE_LD_IMM_HB;
 
    assert id_ex_register.opcode = OPCODE_LD_IMM_HB;
 
    assert id_ex_register.immediate = x"5500";
 
    assert id_ex_register.immediate = x"5500";
 
    assert id_ex_register.cond = COND_UNCONDITIONAL;
 
    assert id_ex_register.cond = COND_UNCONDITIONAL;
 
    assert rx_addr = TB_RX_ADDR_TEST_VALUE;
 
    assert rx_addr = x"1";
 
    assert id_ex_register.rX_addr = TB_RX_ADDR_TEST_VALUE;
 
    assert id_ex_register.rX_addr = x"1";
 
    assert id_ex_register.rX = TB_RX_TEST_VALUE;
 
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
 
 
 
 
 
 
 
    -- test case: OPCODE_LD_DISP
 
 
 
    if_id_register.ir <= "101"& "000" & "11" & x"1" & x"2";
 
 
 
    wait for TB_CLOCK;
 
 
 
    assert id_ex_register.opcode = OPCODE_LD_DISP;
 
 
 
    assert id_ex_register.rX_addr = x"1";
 
 
 
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
 
 
 
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
 
 
 
    assert id_ex_register.rZ = TB_R3_TEST_VALUE;
 
 
 
    assert id_ex_register.cond = TB_COND_TEST_VALUE;
 
 
 
    assert rx_addr = x"1";
 
 
 
    assert ry_addr = x"2";
 
 
 
    assert rz_addr = x"3";
 
 
 
 
 
 
 
    -- test case: OPCODE_LD_DISP_MS
 
 
 
    if_id_register.ir <= "110" & "000" & "11" & x"1" & x"2";
 
 
 
    wait for TB_CLOCK;
 
 
 
    assert id_ex_register.opcode = OPCODE_LD_DISP_MS;
 
 
 
    assert id_ex_register.rX_addr = x"1";
 
 
 
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
 
 
 
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
 
 
 
    assert id_ex_register.rZ = TB_R3_TEST_VALUE;
 
 
 
    assert id_ex_register.cond = TB_COND_TEST_VALUE;
 
 
 
    assert rx_addr = x"1";
 
 
 
    assert ry_addr = x"2";
 
 
 
    assert rz_addr = x"3";
 
 
 
 
 
 
 
    -- test case: OPCODE_LD_REG
 
 
 
    if_id_register.ir <= "00001" & "001" & x"2" & x"1";
 
 
 
    wait for TB_CLOCK;
 
 
 
    assert id_ex_register.opcode = OPCODE_LD_REG;
 
 
 
    assert id_ex_register.rX_addr = x"2";
 
 
 
    assert id_ex_register.rX = TB_R2_TEST_VALUE;
 
 
 
    assert id_ex_register.rY = TB_R1_TEST_VALUE;
 
 
 
    assert id_ex_register.cond = COND_NOT_ZERO;
 
 
 
    assert rx_addr = x"2";
 
 
 
    assert ry_addr = x"1";
 
    wait;                               -- will wait forever
 
    wait;                               -- will wait forever
 
  end process;
 
  end process;
 
 
 
 
 
end;
 
end;
 
 
 
 
 
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