URL https://opencores.org/ocsvn/rise/rise/trunk

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[/] [rise/] [trunk/] [vhdl/] [wb_stage.vhd] - Diff between revs 95 and 106

Rev 95	Rev 106
Line 66...	Line 66...
`else`	`else`

`-- write back of register value. --`	`-- write back of register value. --`
`dreg_addr <= mem_wb_register.dreg_addr;`	`dreg_addr <= mem_wb_register.dreg_addr;`
`if mem_wb_register.aluop1(ALUOP1_WB_REG_BIT) = '1' then`	`if mem_wb_register.aluop1(ALUOP1_WB_REG_BIT) = '1' then`
	`if mem_wb_register.aluop1(ALUOP1_LD_MEM_BIT) = '1' then`
	`dreg <= mem_wb_register.mem_reg;`
	`else`
`dreg <= mem_wb_register.reg;`	`dreg <= mem_wb_register.reg;`
	`end if;`
`dreg_enable <= '1';`	`dreg_enable <= '1';`
`clear_reg_lock0 <= '1';`	`clear_reg_lock0 <= '1';`
`lock_reg_addr0 <= mem_wb_register.dreg_addr;`	`lock_reg_addr0 <= mem_wb_register.dreg_addr;`
`elsif mem_wb_register.aluop1(ALUOP1_LD_MEM_BIT) = '1' then`
`dreg <= mem_wb_register.mem_reg;`
`else`	`else`
`dreg_enable <= '0';`	`dreg_enable <= '0';`
`dreg <= (others => 'X');`	`dreg <= (others => 'X');`
`clear_reg_lock0 <= '0';`	`clear_reg_lock0 <= '0';`
`lock_reg_addr0 <= (others => 'X');`	`lock_reg_addr0 <= (others => 'X');`