| Line 49... |
Line 49... |
clear_out <= '0'; -- clear_out output is unused at the moment.
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clear_out <= '0'; -- clear_out output is unused at the moment.
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process (reset, mem_wb_register)
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process (reset, mem_wb_register)
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begin
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begin
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if reset = '0' then
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if reset = '0' then
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sr_enable <= '0';
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lr_enable <= '0';
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dreg_enable <= '0';
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clear_reg_lock0 <= '0';
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clear_reg_lock0 <= '0';
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lock_reg_addr0 <= (others => '-');
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lock_reg_addr0 <= (others => 'X');
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clear_reg_lock1 <= '0';
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clear_reg_lock1 <= '0';
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lock_reg_addr1 <= (others => '-');
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lock_reg_addr1 <= (others => 'X');
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dreg_addr <= (others => '-');
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dreg_enable <= '0';
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dreg <= (others => '-');
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dreg_addr <= (others => 'X');
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lr <= (others => '-');
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dreg <= (others => 'X');
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sr <= (others => '-');
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lr_enable <= '0';
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lr <= (others => 'X');
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sr_enable <= '0';
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sr <= (others => 'X');
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else
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else
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-- write back of register value. --
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-- write back of register value. --
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dreg_addr <= mem_wb_register.dreg_addr;
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dreg_addr <= mem_wb_register.dreg_addr;
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if mem_wb_register.aluop1(ALUOP1_WB_REG_BIT) = '1' then
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if mem_wb_register.aluop1(ALUOP1_WB_REG_BIT) = '1' then
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| Line 74... |
Line 73... |
clear_reg_lock0 <= '1';
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clear_reg_lock0 <= '1';
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lock_reg_addr0 <= mem_wb_register.dreg_addr;
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lock_reg_addr0 <= mem_wb_register.dreg_addr;
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elsif mem_wb_register.aluop1(ALUOP1_LD_MEM_BIT) = '1' then
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elsif mem_wb_register.aluop1(ALUOP1_LD_MEM_BIT) = '1' then
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dreg <= mem_wb_register.mem_reg;
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dreg <= mem_wb_register.mem_reg;
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else
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else
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dreg <= (others => '0');
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dreg_enable <= '0';
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dreg_enable <= '0';
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dreg <= (others => 'X');
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clear_reg_lock0 <= '0';
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clear_reg_lock0 <= '0';
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lock_reg_addr0 <= (others => '-');
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lock_reg_addr0 <= (others => 'X');
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end if;
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end if;
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-- we have only one lock register.
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-- we have only one lock register.
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assert mem_wb_register.aluop2(ALUOP2_SR_BIT) = '0' or mem_wb_register.aluop2(ALUOP2_LR_BIT) = '0';
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assert mem_wb_register.aluop2(ALUOP2_SR_BIT) = '0' or mem_wb_register.aluop2(ALUOP2_LR_BIT) = '0';
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clear_reg_lock1 <= '0';
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clear_reg_lock1 <= '0';
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lock_reg_addr1 <= (others => '-');
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lock_reg_addr1 <= (others => 'X');
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-- write back of LR --
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-- write back of LR --
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if mem_wb_register.aluop2(ALUOP2_LR_BIT) = '1' then
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if mem_wb_register.aluop2(ALUOP2_LR_BIT) = '1' then
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lr <= mem_wb_register.lr;
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lr <= mem_wb_register.lr;
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lr_enable <= '1';
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lr_enable <= '1';
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clear_reg_lock1 <= '1';
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clear_reg_lock1 <= '1';
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