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[/] [rise/] [trunk/] [vhdl/] [wb_stage.vhd] - Diff between revs 91 and 95
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| Rev 91 |
Rev 95 |
| Line 47... |
Line 47... |
begin -- wb_stage_rtl
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begin -- wb_stage_rtl
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clear_out <= '0'; -- clear_out output is unused at the moment.
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clear_out <= '0'; -- clear_out output is unused at the moment.
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process (reset, mem_wb_register)
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process (reset, mem_wb_register)
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variable sr_test_value : REGISTER_T;
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begin
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begin
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if reset = '0' then
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if reset = '0' then
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clear_reg_lock0 <= '0';
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clear_reg_lock0 <= '0';
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lock_reg_addr0 <= (others => 'X');
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lock_reg_addr0 <= (others => 'X');
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clear_reg_lock1 <= '0';
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clear_reg_lock1 <= '0';
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| Line 101... |
Line 100... |
-- write back of SR --
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-- write back of SR --
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if mem_wb_register.aluop2(ALUOP2_SR_BIT) = '1' then
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if mem_wb_register.aluop2(ALUOP2_SR_BIT) = '1' then
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-- calculate SR value
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-- calculate SR value
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sr <= mem_wb_register.sr;
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sr <= mem_wb_register.sr;
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if mem_wb_register.aluop1(ALUOP1_LD_MEM_BIT) = '1' then
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if mem_wb_register.aluop1(ALUOP1_LD_MEM_BIT) = '1' then
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sr_test_value := mem_wb_register.mem_reg;
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if mem_wb_register.mem_reg = CONV_STD_LOGIC_VECTOR(0, REGISTER_WIDTH) then
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else
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sr_test_value := mem_wb_register.reg;
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end if;
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if sr_test_value = CONV_STD_LOGIC_VECTOR(0, REGISTER_WIDTH) then
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sr( SR_REGISTER_ZERO ) <= '1';
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sr( SR_REGISTER_ZERO ) <= '1';
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end if;
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end if;
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if sr_test_value( REGISTER_WIDTH - 1 ) = '1' then
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if mem_wb_register.mem_reg( REGISTER_WIDTH - 1 ) = '1' then
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sr( SR_REGISTER_NEGATIVE ) <= '1';
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sr( SR_REGISTER_NEGATIVE ) <= '1';
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end if;
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end if;
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end if;
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sr_enable <= '1';
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sr_enable <= '1';
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clear_reg_lock1 <= '1';
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clear_reg_lock1 <= '1';
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lock_reg_addr1 <= SR_REGISTER_ADDR;
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lock_reg_addr1 <= SR_REGISTER_ADDR;
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else
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else
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sr <= ( others => 'X' );
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sr <= ( others => 'X' );
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