Subversion Repositories robust_axi2apb

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This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.

This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.

It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.

It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.

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RobustVerilog generic AXI to APB bridge

RobustVerilog generic AXI to APB bridge

In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).

In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).

The default definition file def_axi2apb.txt generates a bridge with 8 APB slaves.

The default definition file def_axi2apb.txt generates a bridge with 8 APB slaves.

Changing the interconnect parameters should be made only in def_axi2apb.txt in the src/base directory (changing slave num etc.).

Changing the interconnect parameters should be made only in def_axi2apb.txt in the src/base directory (changing slave num etc.).