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[/] [robust_axi2apb/] [trunk/] [src/] [base/] [axi2apb.v] - Diff between revs 4 and 6

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Rev 4 Rev 6
Line 37... Line 37...
   input              reset;
   input              reset;
 
 
   port               GROUP_APB_AXI;
   port               GROUP_APB_AXI;
 
 
   //apb slaves
   //apb slaves
 
IFDEF TRUE(SLAVE_NUM==1)
 
   port               GROUP_APB3;
 
ELSE TRUE(SLAVE_NUM==1)
   output             penable;
   output             penable;
   output             pwrite;
   output             pwrite;
   output [ADDR_BITS-1:0] paddr;
   output [ADDR_BITS-1:0] paddr;
   output [31:0]          pwdata;
   output [31:0]          pwdata;
 
 
   output                 pselSX;
   output                 pselSX;
 
 
   input [31:0]           prdataSX;
   input [31:0]           prdataSX;
 
 
   input                  preadySX;
   input                  preadySX;
 
 
   input                  pslverrSX;
   input                  pslverrSX;
 
ENDIF TRUE(SLAVE_NUM==1)
 
 
 
 
 
 
   wire                   GROUP_APB3;
   wire                   GROUP_APB3;
 
 
Line 111... Line 111...
                                         .WGROUP_APB_AXI_W(WGROUP_APB_AXI_W),
                                         .WGROUP_APB_AXI_W(WGROUP_APB_AXI_W),
                                         .BGROUP_APB_AXI_B(BGROUP_APB_AXI_B),
                                         .BGROUP_APB_AXI_B(BGROUP_APB_AXI_B),
                                         STOMP ,
                                         STOMP ,
                                         );
                                         );
 
 
   CREATE axi2apb_mux.v
 
     PREFIX_axi2apb_mux PREFIX_axi2apb_mux(
 
                                           .clk(clk),
 
                                           .reset(reset),
 
                                           .cmd_addr(cmd_addr),
 
                                           .psel(psel),
 
                                           .prdata(prdata),
 
                                           .pready(pready),
 
                                           .pslverr(pslverr),
 
                                           .pselSX(pselSX),
 
                                           .preadySX(preadySX),
 
                                           .pslverrSX(pslverrSX),
 
                                           .prdataSX(prdataSX),
 
                                           STOMP ,
 
                                           );
 
 
 
 
 
   CREATE axi2apb_ctrl.v
   CREATE axi2apb_ctrl.v
     PREFIX_axi2apb_ctrl PREFIX_axi2apb_ctrl(
     PREFIX_axi2apb_ctrl PREFIX_axi2apb_ctrl(
                                             .clk(clk),
                                             .clk(clk),
Line 144... Line 129...
                                             .pwrite(pwrite),
                                             .pwrite(pwrite),
                                             .pready(pready)
                                             .pready(pready)
                                             );
                                             );
 
 
 
 
 
IFDEF TRUE(SLAVE_NUM>1)
 
   CREATE axi2apb_mux.v
 
     PREFIX_axi2apb_mux PREFIX_axi2apb_mux(
 
                                           .clk(clk),
 
                                           .reset(reset),
 
                                           .cmd_addr(cmd_addr),
 
                                           .psel(psel),
 
                                           .prdata(prdata),
 
                                           .pready(pready),
 
                                           .pslverr(pslverr),
 
                                           .pselSX(pselSX),
 
                                           .preadySX(preadySX),
 
                                           .pslverrSX(pslverrSX),
 
                                           .prdataSX(prdataSX),
 
                                           STOMP ,
 
                                           );
 
ENDIF TRUE(SLAVE_NUM>1)
 
 
endmodule
endmodule
 
 
 
 
 
 
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