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[/] [robust_axi2apb/] [trunk/] [src/] [gen/] [prgen_fifo.v] - Diff between revs 4 and 11

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<##//////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////          eyal@provartec.com                                 ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
////  Downloaded from: http://www.opencores.org                  ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
////                                                             ////
//////////////////////////////////////////////////////////////////##>
/////////////////////////////////////////////////////////////////////
 
 
 
IFDEF STUB
 
OUTFILE prgen_fifo_stub.v
 
module prgen_fifo_stub(PORTS);
 
ELSE STUB
OUTFILE prgen_fifo.v
OUTFILE prgen_fifo.v
 
 
ITER DX 1 15
 
module prgen_fifo(PORTS);
module prgen_fifo(PORTS);
 
ENDIF STUB
 
 
   parameter                  WIDTH      = 8;
   parameter                  WIDTH      = 8;
   parameter                  DEPTH_FULL = 8;
   parameter                  DEPTH_FULL = 8;
 
 
   parameter                  SINGLE     = DEPTH_FULL == 1;
   parameter                  SINGLE     = DEPTH_FULL == 1;
   parameter                  DEPTH      = SINGLE ? 1 : DEPTH_FULL -1;
   parameter                  DEPTH      = SINGLE ? 1 : DEPTH_FULL -1;
   parameter                  DEPTH_BITS =
   parameter                  DEPTH_BITS =
                              (DEPTH <= EXPR(2^DX)) ? DX :
                              (DEPTH <= 2)   ? 1 :
                              0; //0 is ilegal
                              (DEPTH <= 4)   ? 2 :
 
                              (DEPTH <= 8)   ? 3 :
 
                              (DEPTH <= 16)  ? 4 :
 
                              (DEPTH <= 32)  ? 5 :
 
                              (DEPTH <= 64)  ? 6 :
 
                              (DEPTH <= 128) ? 7 :
 
                              (DEPTH <= 256) ? 8 :
 
                              (DEPTH <= 512) ? 9 : 0; //0 is ilegal
 
 
   parameter                  LAST_LINE  = DEPTH-1;
   parameter                  LAST_LINE  = DEPTH-1;
 
 
 
 
 
 
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   input                      push;
   input                      push;
   input                      pop;
   input                      pop;
   input [WIDTH-1:0]           din;
   input [WIDTH-1:0]           din;
   output [WIDTH-1:0]          dout;
   output [WIDTH-1:0]          dout;
 
   IF STUB output [DEPTH_BITS:0] fullness;
   output                     empty;
   output                     empty;
   output                     full;
   output                     full;
 
 
 
 
   wire                       reg_push;
   wire                       reg_push;
   wire                       reg_pop;
   wire                       reg_pop;
   wire                       fifo_push;
   wire                       fifo_push;
   wire                       fifo_pop;
   wire                       fifo_pop;
 
 
   reg [DEPTH-1:0]             fullness_in;
   reg [DEPTH-1:0]             full_mask_in;
   reg [DEPTH-1:0]             fullness_out;
   reg [DEPTH-1:0]             full_mask_out;
   reg [DEPTH-1:0]             fullness;
   reg [DEPTH-1:0]             full_mask;
   reg [WIDTH-1:0]             fifo [DEPTH-1:0];
   reg [WIDTH-1:0]             fifo [DEPTH-1:0];
   wire                       fifo_empty;
   wire                       fifo_empty;
   wire                       next;
   wire                       next;
   reg [WIDTH-1:0]             dout;
   reg [WIDTH-1:0]             dout;
   reg                        dout_empty;
   reg                        dout_empty;
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   always @(posedge clk)
   always @(posedge clk)
     if (fifo_push)
     if (fifo_push)
       fifo[ptr_in] <= #FFD din;
       fifo[ptr_in] <= #FFD din;
 
 
 
 
   always @(*)
   always @(/*AUTOSENSE*/fifo_push or ptr_in)
     begin
     begin
        fullness_in = {DEPTH{1'b0}};
        full_mask_in = {DEPTH{1'b0}};
        fullness_in[ptr_in] = fifo_push;
        full_mask_in[ptr_in] = fifo_push;
     end
     end
 
 
   always @(*)
   always @(/*AUTOSENSE*/fifo_pop or ptr_out)
     begin
     begin
        fullness_out = {DEPTH{1'b0}};
        full_mask_out = {DEPTH{1'b0}};
        fullness_out[ptr_out] = fifo_pop;
        full_mask_out[ptr_out] = fifo_pop;
     end
     end
 
 
   always @(posedge clk or posedge reset)
   always @(posedge clk or posedge reset)
     if (reset)
     if (reset)
       fullness <= #FFD {DEPTH{1'b0}};
       full_mask <= #FFD {DEPTH{1'b0}};
     else if (fifo_push | fifo_pop)
     else if (fifo_push | fifo_pop)
       fullness <= #FFD (fullness & (~fullness_out)) | fullness_in;
       full_mask <= #FFD (full_mask & (~full_mask_out)) | full_mask_in;
 
 
 
 
   assign next       = |fullness;
   assign next       = |full_mask;
   assign fifo_empty = ~next;
   assign fifo_empty = ~next;
   assign empty      = fifo_empty & dout_empty;
   assign empty      = fifo_empty & dout_empty;
   assign full       = SINGLE ? !dout_empty : &fullness;
   assign full       = SINGLE ? !dout_empty : &full_mask;
 
 
 
 
 
 
 
IFDEF STUB
 
  reg [DEPTH_BITS:0] fullness;
 
 
 
   always @(posedge clk or posedge reset)
 
     if (reset)
 
       fullness <= #FFD {DEPTH_BITS+1{1'b0}};
 
     else if (push | pop)
 
       fullness <= #FFD fullness + push - pop;
 
 
 
   wire              overflow  = full & fifo_push & (~fifo_pop);
 
   wire              underflow = empty & fifo_pop & (~fifo_push);
 
 
 
   always @(posedge overflow)
 
     begin
 
        #1;
 
        if (overflow)
 
          begin
 
             $display("-E-%m - overflow.\tTime: %0d ns", $time);
 
             #1000;
 
             $finish;
 
          end
 
     end
 
   always @(posedge underflow)
 
     begin
 
        #1;
 
        if (underflow)
 
          begin
 
             $display("-E-%m - underflow.\tTime: %0d ns", $time);
 
             #1000;
 
             $finish;
 
          end
 
     end
 
ENDIF STUB
 
 
endmodule
endmodule
 
 
 
 
 
 
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