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Line 2... |
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SWAP #FFD #1 ##flip-flop delay
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SWAP #FFD #1 ##flip-flop delay
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SWAP PREFIX fabric_MASTER_NUM_SLAVE_NUM ##prefix for all module and file names
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SWAP PREFIX fabric_MASTER_NUM_SLAVE_NUM ##prefix for all module and file names
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##fabric 0
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BUILD
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SWAP MASTER_NUM 3 ##number of masters
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SWAP MASTER_NUM 3 ##number of masters
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SWAP SLAVE_NUM 8 ##number of slaves
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SWAP SLAVE_NUM 6 ##number of slaves
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##DEFINE DEF_DECERR_SLV ##use interanl decode slave error
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DEFINE DEF_DECERR_SLV ##use interanl decode slave error
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SWAP ID_BITS 2 ##AXI ID bits
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SWAP ID_BITS 3 ##AXI ID bits
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LOOP M0_IDX 1 ##number of IDs for master 0
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LOOP M0_IDX 2 ##number of IDs for master 0
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SWAP ID_M0_ID0 ID_BITS'b00 ##master 0 ID0
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SWAP ID_M0_ID0 ID_BITS'b000 ##master 0 ID0
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SWAP ID_M0_ID1 ID_BITS'b001 ##master 0 ID1
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LOOP M1_IDX 1 ##number of IDs for master 1
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LOOP M1_IDX 1 ##number of IDs for master 1
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SWAP ID_M1_ID0 ID_BITS'b01 ##master 1 ID0
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SWAP ID_M1_ID0 ID_BITS'b011 ##master 1 ID0
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LOOP M2_IDX 1 ##number of IDs for master 2
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LOOP M2_IDX 1 ##number of IDs for master 2
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SWAP ID_M2_ID0 ID_BITS'b10 ##master 2 ID0
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SWAP ID_M2_ID0 ID_BITS'b101 ##master 2 ID0
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SWAP CMD_DEPTH 8 ##AXI command depth for read and write
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SWAP CMD_DEPTH 8 ##AXI command depth for read and write
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SWAP DATA_BITS 64 ##AXI data bits
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SWAP DATA_BITS 64 ##AXI data bits
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SWAP ADDR_BITS 32 ##AXI address bits
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SWAP ADDR_BITS 32 ##AXI address bits
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SWAP USER_BITS 4 ##AXI user bits
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SWAP USER_BITS 4 ##AXI user bits
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ENDBUILD
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##fabric 1
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BUILD
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SWAP MASTER_NUM 1 ##number of masters
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SWAP SLAVE_NUM 3 ##number of slaves
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DEFINE DEF_DECERR_SLV ##use interanl decode slave error
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SWAP ID_BITS 2 ##AXI ID bits
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LOOP M0_IDX 3 ##number of IDs for master 0
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SWAP ID_M0_ID0 ID_BITS'b00 ##master 0 ID0
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SWAP ID_M0_ID1 ID_BITS'b01 ##master 0 ID1
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SWAP ID_M0_ID2 ID_BITS'b11 ##master 0 ID2
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SWAP CMD_DEPTH 4 ##AXI command depth for read and write
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SWAP DATA_BITS 32 ##AXI data bits
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SWAP ADDR_BITS 24 ##AXI address bits
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SWAP USER_BITS 0 ##AXI user bits
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ENDBUILD
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