URL
https://opencores.org/ocsvn/robust_axi_fabric/robust_axi_fabric/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 8 |
Rev 9 |
Line 42... |
Line 42... |
input [ID_BITS-1:0] MMX_AID;
|
input [ID_BITS-1:0] MMX_AID;
|
output [SLV_BITS-1:0] MMX_ASLV;
|
output [SLV_BITS-1:0] MMX_ASLV;
|
output MMX_AIDOK;
|
output MMX_AIDOK;
|
|
|
parameter DEC_MSB = ADDR_BITS - 1;
|
parameter DEC_MSB = ADDR_BITS - 1;
|
parameter DEC_LSB = ADDR_BITS - MSTR_BITS;
|
parameter DEC_LSB = ADDR_BITS - SLV_BITS;
|
|
|
reg [SLV_BITS-1:0] MMX_ASLV;
|
reg [SLV_BITS-1:0] MMX_ASLV;
|
reg MMX_AIDOK;
|
reg MMX_AIDOK;
|
|
|
LOOP MX
|
LOOP MX
|
always @(MMX_AADDR or MMX_AIDOK)
|
always @(MMX_AADDR or MMX_AIDOK)
|
begin
|
begin
|
case ({MMX_AIDOK, MMX_AADDR[DEC_MSB:DEC_LSB]})
|
case ({MMX_AIDOK, MMX_AADDR[DEC_MSB:DEC_LSB]})
|
{1'b1, BIN(SX MSTR_BITS)} : MMX_ASLV = 'dSX;
|
{1'b1, BIN(SX SLV_BITS)} : MMX_ASLV = 'dSX;
|
default : MMX_ASLV = 'dSERR;
|
default : MMX_ASLV = 'dSERR;
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(MMX_AID)
|
always @(MMX_AID)
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.