URL https://opencores.org/ocsvn/robust_axi_fabric/robust_axi_fabric/trunk

Subversion Repositories robust_axi_fabric

[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [ic_dec.v] - Diff between revs 19 and 20

Rev 19	Rev 20
Line 43...	Line 43...
`parameter DEC_LSB = ADDR_BITS - SLV_BITS;`	`parameter DEC_LSB = ADDR_BITS - SLV_BITS;`

`reg [SLV_BITS-1:0] MMX_ASLV;`	`reg [SLV_BITS-1:0] MMX_ASLV;`
`reg MMX_AIDOK;`	`reg MMX_AIDOK;`

	`wire [DEC_MSB:DEC_LSB] MMX_AADDR_DEC;`


	`assign MMX_AADDR_DEC = MMX_AADDR[DEC_MSB:DEC_LSB];`

`LOOP MX`	`LOOP MX`
`always @(MMX_AADDR or MMX_AIDOK)`	`always @(MMX_AADDR or MMX_AIDOK)`
`begin`	`begin`
`IFDEF TRUE(SLAVE_NUM==1)`	`IFDEF TRUE(SLAVE_NUM==1)`
`case (MMX_AIDOK)`	`case (MMX_AIDOK)`
`1'b1 : MMX_ASLV = SLV_BITS'd0;`	`1'b1 : MMX_ASLV = SLV_BITS'd0;`
`ELSE TRUE(SLAVE_NUM==1)`	`ELSE TRUE(SLAVE_NUM==1)`
`case ({MMX_AIDOK, MMX_AADDR[DEC_MSB:DEC_LSB]})`	`case ({MMX_AIDOK, MMX_AADDR_DEC})`
`{1'b1, BIN(SX SLV_BITS)} : MMX_ASLV = SLV_BITS'dSX;`	`{1'b1, BIN(SX SLV_BITS)} : MMX_ASLV = SLV_BITS'dSX;`
`ENDIF TRUE(SLAVE_NUM==1)`	`ENDIF TRUE(SLAVE_NUM==1)`
`default : MMX_ASLV = SLV_BITS'dSERR;`	`default : MMX_ASLV = SLV_BITS'dSERR;`
`endcase`	`endcase`
`end`	`end`