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https://opencores.org/ocsvn/rs232_interface/rs232_interface/trunk
[/] [rs232_interface/] [trunk/] [uart.vhd] - Diff between revs 5 and 6
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-- Create Date: 21:12:48 05/06/2010
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-- Creation Date: 21:12:48 05/06/2010
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-- Module Name: UART - Behavioral
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-- Module Name: RS232/UART Interface - Behavioral
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-- Used TAB of 4 Spaces
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-- Used TAB of 4 Spaces
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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signal tx_fsm : state;
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signal tx_fsm : state;
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signal clock_en : std_logic;
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signal clock_en : std_logic;
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-- Data Temp
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-- Data Temp
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signal data_cnt_tx : std_logic_vector(2 downto 0) := "000";
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signal data_cnt_tx : std_logic_vector(2 downto 0) := "000";
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signal data_cnt_rx : std_logic_vector(2 downto 0) := "000";
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signal data_cnt_rx : std_logic_vector(2 downto 0);
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signal rx_data_tmp : std_logic_vector(7 downto 0);
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signal rx_data_tmp : std_logic_vector(7 downto 0);
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signal tx_data_tmp : std_logic_vector(7 downto 0);
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signal tx_data_tmp : std_logic_vector(7 downto 0);
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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rx_fsm <= idle;
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rx_fsm <= idle;
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rx_ready <= '0';
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rx_ready <= '0';
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rx_data <= (others=>'0');
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rx_data <= (others=>'0');
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data_cnt_rx <= (others=>'0');
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data_cnt_rx <= (others=>'0');
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rx_data_tmp <= (others=>'0');
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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