| Line 18... |
Line 18... |
clk : in std_logic; -- Main clock
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clk : in std_logic; -- Main clock
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rst : in std_logic; -- Main reset
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rst : in std_logic; -- Main reset
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-- External Interface
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-- External Interface
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rx : in std_logic; -- RS232 received serial data
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rx : in std_logic; -- RS232 received serial data
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tx : out std_logic; -- RS232 transmitted serial data
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tx : out std_logic; -- RS232 transmitted serial data
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-- RS232/UART Configuration
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par_en : in std_logic; -- Parity bit enable
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-- uPC Interface
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-- uPC Interface
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tx_req : in std_logic; -- Request SEND of data
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tx_req : in std_logic; -- Request SEND of data
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tx_end : out std_logic; -- Data SENDED
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tx_end : out std_logic; -- Data SENDED
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tx_data : in std_logic_vector(7 downto 0); -- Data to transmit
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tx_data : in std_logic_vector(7 downto 0); -- Data to transmit
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rx_ready : out std_logic; -- Received data ready to uPC read
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rx_ready : out std_logic; -- Received data ready to uPC read
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| Line 30... |
Line 32... |
end uart;
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end uart;
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architecture Behavioral of uart is
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architecture Behavioral of uart is
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-- Constants
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-- Constants
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constant uart_idle : std_logic := '1';
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constant UART_IDLE : std_logic := '1';
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constant uart_start : std_logic := '0';
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constant UART_START : std_logic := '0';
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constant PARITY_EN : std_logic := '1';
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constant RST_LVL : std_logic := '1';
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-- Types
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-- Types
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type state is (idle,data,stop1,stop2);
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type state is (idle,data,parity,stop1,stop2); -- Stop1 and Stop2 are inter frame gap
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-- Signals
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-- Signals
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signal rx_fsm : state;
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signal rx_fsm : state; -- Control of reception
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signal tx_fsm : state;
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signal tx_fsm : state; -- Control of transmission
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signal clock_en : std_logic;
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signal clock_en : std_logic; -- Internal clock enable
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-- Data Temp
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-- RX Data Temp
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signal data_cnt_tx : std_logic_vector(2 downto 0) := "000";
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signal rx_par_bit : std_logic;
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signal data_cnt_rx : std_logic_vector(2 downto 0);
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signal rx_data_tmp : std_logic_vector(7 downto 0);
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signal rx_data_tmp : std_logic_vector(7 downto 0);
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signal rx_data_cnt : std_logic_vector(2 downto 0);
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-- TX Data Temp
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signal tx_par_bit : std_logic;
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signal tx_data_tmp : std_logic_vector(7 downto 0);
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signal tx_data_tmp : std_logic_vector(7 downto 0);
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signal tx_data_cnt : std_logic_vector(2 downto 0);
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begin
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begin
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clock_manager:process(clk)
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clock_manager:process(clk)
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variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);
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variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);
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| Line 62... |
Line 70... |
else
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else
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clock_en <= '0';
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clock_en <= '0';
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counter := counter + 1;
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counter := counter + 1;
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end if;
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end if;
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-- Reset condition
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-- Reset condition
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if rst = '1' then
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if rst = RST_LVL then
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counter := 0;
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counter := 0;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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| Line 75... |
Line 83... |
begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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if clock_en = '1' then
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if clock_en = '1' then
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-- Default values
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-- Default values
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tx_end <= '0';
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tx_end <= '0';
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tx <= uart_idle;
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tx <= UART_IDLE;
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-- FSM description
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-- FSM description
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case tx_fsm is
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case tx_fsm is
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-- Wait to transfer data
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-- Wait to transfer data
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when idle =>
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when idle =>
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-- Send Init Bit
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-- Send Init Bit
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if tx_req = '1' then
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if tx_req = '1' then
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tx <= uart_start;
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tx <= UART_START;
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tx_data_tmp <= tx_data;
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tx_data_tmp <= tx_data;
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tx_fsm <= data;
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tx_fsm <= data;
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data_cnt_tx <= (others=>'1');
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tx_data_cnt <= (others=>'1');
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tx_par_bit <= '0';
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end if;
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end if;
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-- Data receive
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-- Data receive
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when data =>
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when data =>
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tx <= tx_data_tmp(0);
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tx <= tx_data_tmp(0);
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if data_cnt_tx = 0 then
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tx_par_bit <= tx_par_bit xor tx_data_tmp(0);
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if tx_data_cnt = 0 then
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if par_en = PARITY_EN then
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tx_fsm <= parity;
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else
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tx_fsm <= stop1;
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tx_fsm <= stop1;
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data_cnt_tx <= (others=>'1');
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end if;
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tx_data_cnt <= (others=>'1');
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else
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else
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tx_data_tmp <= '0' & tx_data_tmp(7 downto 1);
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tx_data_tmp <= '0' & tx_data_tmp(7 downto 1);
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data_cnt_tx <= data_cnt_tx - 1;
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tx_data_cnt <= tx_data_cnt - 1;
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end if;
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end if;
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when parity =>
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tx <= tx_par_bit;
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tx_fsm <= stop1;
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-- End of communication
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-- End of communication
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when stop1 =>
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when stop1 =>
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-- Send Stop Bit
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-- Send Stop Bit
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tx <= uart_idle;
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tx <= UART_IDLE;
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tx_fsm <= stop2;
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tx_fsm <= stop2;
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when stop2 =>
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when stop2 =>
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-- Send Stop Bit
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-- Send Stop Bit
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tx_end <= '1';
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tx_end <= '1';
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tx <= uart_idle;
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tx <= UART_IDLE;
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tx_fsm <= idle;
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tx_fsm <= idle;
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-- Invalid States
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-- Invalid States
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when others => null;
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when others => null;
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end case;
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end case;
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-- Reset condition
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-- Reset condition
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if rst = '1' then
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if rst = RST_LVL then
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tx_fsm <= idle;
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tx_fsm <= idle;
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tx_par_bit <= '0';
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tx_data_tmp <= (others=>'0');
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tx_data_tmp <= (others=>'0');
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tx_data_cnt <= (others=>'0');
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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| Line 129... |
Line 148... |
rx_ready <= '0';
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rx_ready <= '0';
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-- FSM description
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-- FSM description
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case rx_fsm is
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case rx_fsm is
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-- Wait to transfer data
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-- Wait to transfer data
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when idle =>
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when idle =>
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if rx = uart_start then
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if rx = UART_START then
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rx_fsm <= data;
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rx_fsm <= data;
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end if;
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end if;
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data_cnt_rx <= (others=>'0');
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rx_par_bit <= '0';
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rx_data_cnt <= (others=>'0');
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-- Data receive
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-- Data receive
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when data =>
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when data =>
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if data_cnt_rx = 7 then
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-- Check data to generate parity
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rx_fsm <= idle;
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if par_en = PARITY_EN then
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rx_ready <= '1';
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rx_par_bit <= rx_par_bit xor rx;
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end if;
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if rx_data_cnt = 7 then
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-- Data path
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rx_data(7) <= rx;
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rx_data(7) <= rx;
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for i in 0 to 6 loop
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for i in 0 to 6 loop
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rx_data(i) <= rx_data_tmp(6-i);
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rx_data(i) <= rx_data_tmp(6-i);
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end loop;
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end loop;
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-- With parity verification
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if par_en = PARITY_EN then
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rx_fsm <= parity;
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-- Without parity verification
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else
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rx_ready <= '1';
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rx_fsm <= idle;
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end if;
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else
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else
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rx_data_tmp <= rx_data_tmp(6 downto 0) & rx;
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rx_data_tmp <= rx_data_tmp(6 downto 0) & rx;
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data_cnt_rx <= data_cnt_rx + 1;
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rx_data_cnt <= rx_data_cnt + 1;
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end if;
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when parity =>
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-- Check received parity
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rx_fsm <= idle;
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if rx_par_bit = rx then
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rx_ready <= '1';
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end if;
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end if;
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when others => null;
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when others => null;
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end case;
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end case;
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-- Reset condition
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-- Reset condition
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if rst = '1' then
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if rst = RST_LVL then
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rx_fsm <= idle;
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rx_fsm <= idle;
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rx_ready <= '0';
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rx_ready <= '0';
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rx_data <= (others=>'0');
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rx_data <= (others=>'0');
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data_cnt_rx <= (others=>'0');
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rx_data_tmp <= (others=>'0');
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rx_data_tmp <= (others=>'0');
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rx_data_cnt <= (others=>'0');
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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