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URL https://opencores.org/ocsvn/rs232_with_buffer_and_wb/rs232_with_buffer_and_wb/trunk

Subversion Repositories rs232_with_buffer_and_wb

[/] [rs232_with_buffer_and_wb/] [trunk/] [doc/] [RS232_text.txt] - Diff between revs 40 and 45

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Rev 40 Rev 45
Line 13... Line 13...
76800           |
76800           |
115200          |       8.68 mSec       |       434             |       868             |       1736    |
115200          |       8.68 mSec       |       434             |       868             |       1736    |
230400          |       4.34 mSec       |       217             |       434             |       868             |
230400          |       4.34 mSec       |       217             |       434             |       868             |
 
 
 
 
 
 
 
 
Signal          | bit
 
------------|----------
 
start           | 1
 
data            | 5,6,7,8
 
Partition       | 1
 
stop            | 1, 1.5, 2
 
 
 
 
 
Signals/Interrupts
Signals/Interrupts
        RX Buffer empty
        RX Buffer empty
        RX Buffer full
        RX Buffer full
        TX Buffer empty
        TX Buffer empty
        TX Buffer full
        TX Buffer full
Line 35... Line 25...
Buffers
Buffers
        RX FIFO Buffer 0-64 Word buffer
        RX FIFO Buffer 0-64 Word buffer
        TX FIFO Buffer 0-64 Word buffer
        TX FIFO Buffer 0-64 Word buffer
 
 
After Reset
After Reset
        50MHz 2400bps, 100MHz 4800bps
        50MHz 2400bps, 100MHz 4800bps, 200MHz 9600bps
        1 start bit, 8 data bit, 1 stop bit
        1 start bit, 8 data bit, 1 stop bit
 
 
Componenter
Componenter
        Main()
        uart_top                        : top entity
                RS232
                uart_rx                 : rs232 complient reciever
                        uart_rx
                uart_tx                 : rs232 complient tranmitter
                        uart_tx
                uart_rx_fifo    : buffer for revieved data
                BUFFER
                uart_tx_fifo    : buffer for data to be transmitted
                        rx_fifo
                uart_wb                 : WISHBONE interface
                        tx_fifo
 
                WishBone
 
                        uart_setup
 
                        wb_interface
 
 
 
Addresses
Addresses
        00000000 = rx_fifo(r)(rx_fifo_rst.u) / write tx_fifo(w)(tx_fifo_rst.u)
        00000000 = rx_fifo(r)(rx_fifo_rst.u) / write tx_fifo(w)(tx_fifo_rst.u)
        00000001 = |xxxxxxx|rx enable(r/w)(setup_rst.0)|
        00000001 = |xxxxxxx|rx enable(r/w)(setup_rst.0)|
 
 

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