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https://opencores.org/ocsvn/rs232_with_buffer_and_wb/rs232_with_buffer_and_wb/trunk
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Rev 40 |
Rev 45 |
Line 13... |
Line 13... |
76800 |
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76800 |
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115200 | 8.68 mSec | 434 | 868 | 1736 |
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115200 | 8.68 mSec | 434 | 868 | 1736 |
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230400 | 4.34 mSec | 217 | 434 | 868 |
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230400 | 4.34 mSec | 217 | 434 | 868 |
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Signal | bit
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------------|----------
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start | 1
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data | 5,6,7,8
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Partition | 1
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stop | 1, 1.5, 2
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Signals/Interrupts
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Signals/Interrupts
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RX Buffer empty
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RX Buffer empty
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RX Buffer full
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RX Buffer full
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TX Buffer empty
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TX Buffer empty
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TX Buffer full
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TX Buffer full
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Line 35... |
Line 25... |
Buffers
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Buffers
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RX FIFO Buffer 0-64 Word buffer
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RX FIFO Buffer 0-64 Word buffer
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TX FIFO Buffer 0-64 Word buffer
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TX FIFO Buffer 0-64 Word buffer
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After Reset
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After Reset
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50MHz 2400bps, 100MHz 4800bps
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50MHz 2400bps, 100MHz 4800bps, 200MHz 9600bps
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1 start bit, 8 data bit, 1 stop bit
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1 start bit, 8 data bit, 1 stop bit
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Componenter
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Componenter
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Main()
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uart_top : top entity
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RS232
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uart_rx : rs232 complient reciever
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uart_rx
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uart_tx : rs232 complient tranmitter
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uart_tx
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uart_rx_fifo : buffer for revieved data
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BUFFER
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uart_tx_fifo : buffer for data to be transmitted
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rx_fifo
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uart_wb : WISHBONE interface
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tx_fifo
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WishBone
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uart_setup
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wb_interface
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Addresses
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Addresses
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00000000 = rx_fifo(r)(rx_fifo_rst.u) / write tx_fifo(w)(tx_fifo_rst.u)
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00000000 = rx_fifo(r)(rx_fifo_rst.u) / write tx_fifo(w)(tx_fifo_rst.u)
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00000001 = |xxxxxxx|rx enable(r/w)(setup_rst.0)|
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00000001 = |xxxxxxx|rx enable(r/w)(setup_rst.0)|
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