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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity rx_func is
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port( clk, reset, rx_enable : in std_logic;
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rx : in std_logic;
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word_width : in std_logic_vector(3 downto 0);
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baud_period : in std_logic_vector(15 downto 0);
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use_parity_bit, parity_type : in std_logic;
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stop_bits : in std_logic_vector(1 downto 0);
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idle_line_lvl : in std_logic;
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start_samples : in std_logic_vector(3 downto 0); --How many correct samples should give a start bit
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line_samples : in std_logic_vector(3 downto 0); --How many samples should tip the internal rx value
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data : out std_logic_vector(7 downto 0);
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data_ready : out std_logic;
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parity_error : out std_logic;
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stop_bit_error : out std_logic);
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end entity rx_func;
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architecture behaviour of rx_func is
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type state_type is (idle, data_bit0, data_bit1, data_bit2, data_bit3, data_bit4, data_bit5, data_bit6, data_bit7, parity_bit, stop_bit1, stop_bit2, data_check, data_rdy);
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signal current_state : state_type := idle;
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signal next_state, next_state_rst : state_type;
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signal next_state_from_data_bit4 : state_type;
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signal next_state_from_data_bit5 : state_type;
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signal next_state_from_data_bit6 : state_type;
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signal next_state_from_data_bit7 : state_type;
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signal next_state_from_stop_bit1 : state_type;
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signal sampled_data : std_logic_vector(9 downto 0);-- := "0000000000";
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signal period_count_enable : std_logic;
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signal period_count_q : std_logic_vector(15 downto 0);-- := "0000000000000000";
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signal period_count_d : std_logic_vector(15 downto 0);
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signal baud_tick : std_logic;
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signal period16_count_q : std_logic_vector(11 downto 0);-- := "000000000000";
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signal period16_count_d : std_logic_vector(11 downto 0);
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signal sample_tick : std_logic;
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signal sample_reg_q, sample_reg_start_bit_q : std_logic_vector(3 downto 0);-- := "0000";
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signal sample_reg_start_bit_d, sample_reg_d : std_logic_vector(3 downto 0);
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signal rx_sampled_q : std_logic;-- := '0';
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signal rx_sampled_d : std_logic;
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signal xored_sampled_data_bit_q : std_logic;-- := '0';
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signal xored_sampled_data_bit_d : std_logic;
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begin
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-------------------------
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-- Combinational logic --
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-------------------------
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--State Logic
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next_state <= idle when reset = '1' else
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next_state_rst;
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with current_state select
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next_state_rst <= data_bit0 when idle, --Identifying start bit
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data_bit1 when data_bit0,
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data_bit2 when data_bit1,
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data_bit3 when data_bit2,
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data_bit4 when data_bit3,
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next_state_from_data_bit4 when data_bit4,
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next_state_from_data_bit5 when data_bit5,
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next_state_from_data_bit6 when data_bit6,
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next_state_from_data_bit7 when data_bit7,
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stop_bit1 when parity_bit,
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next_state_from_stop_bit1 when stop_bit1,
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data_check when stop_bit2,
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data_rdy when data_check,
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idle when data_rdy,
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idle when others;
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next_state_from_data_bit4 <= parity_bit when word_width = "0101" and use_parity_bit = '1' else
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stop_bit1 when word_width = "0101" and use_parity_bit = '0' else
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data_bit5;
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next_state_from_data_bit5 <= parity_bit when word_width = "0110" and use_parity_bit = '1' else
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stop_bit1 when word_width = "0110" and use_parity_bit = '0' else
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data_bit6;
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next_state_from_data_bit6 <= parity_bit when word_width = "0111" and use_parity_bit = '1' else
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stop_bit1 when word_width = "0111" and use_parity_bit = '0' else
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data_bit7;
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next_state_from_data_bit7 <= parity_bit when use_parity_bit = '1' else
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stop_bit1;
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next_state_from_stop_bit1 <= stop_bit2 when stop_bits = "10" else
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data_check;
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--Sample logic
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period16_count_d <= period16_count_q + 1 when reset = '0' and period16_count_q /= baud_period(15 downto 4) else
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"000000000001";
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sample_tick <= '1' when period16_count_q = baud_period(15 downto 4) else
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'0';
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--Baud logic
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with current_state select
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period_count_enable <= '0' when idle,
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'0' when data_check,
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'0' when data_rdy,
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'1' when others;
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period_count_d <= period_count_q + 1 when reset = '0' and period_count_q /= baud_period else
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"0000000000000001";
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baud_tick <= '1' when period_count_q = baud_period else
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'0';
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--RX sampled, by saturation counter
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sample_reg_d <= sample_reg_q + 1 when reset = '0' and rx = '1' and sample_reg_q /= line_samples else
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sample_reg_q - 1 when reset = '0' and rx = '0' and sample_reg_q /= "0000" else
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sample_reg_q when reset = '0' else
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"0000";
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rx_sampled_d <= '1' when reset = '0' and sample_reg_q = line_samples else
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'0' when reset = '0' and sample_reg_q = "0000" else
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rx_sampled_q;
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sample_reg_start_bit_d <= sample_reg_start_bit_q + 1 when reset = '0' and rx /= idle_line_lvl and sample_reg_start_bit_q /= start_samples else
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sample_reg_start_bit_q - 1 when reset = '0' and rx = idle_line_lvl and sample_reg_start_bit_q /= "0000" else
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sample_reg_start_bit_q when reset = '0' else
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"0000";
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--Parity bit
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with current_state select
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xored_sampled_data_bit_d <= '0' when idle,
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xored_sampled_data_bit_q when stop_bit1,
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xored_sampled_data_bit_q when stop_bit2,
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xored_sampled_data_bit_q when data_check,
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xored_sampled_data_bit_q xor rx_sampled_q when others;
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--Reciving status signals
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data_ready <= '1' when current_state = data_rdy else
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'0';
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parity_error <= '1' when xored_sampled_data_bit_q /= parity_type and current_state = data_check else
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'0';
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stop_bit_error <= '1' when current_state = data_check and (sampled_data(8) /= idle_line_lvl or (sampled_data(9) /= idle_line_lvl and stop_bits = "10")) else
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'0';
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--------------------
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-- Register logic --
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--------------------
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register_logic : process(clk, reset, rx_enable, period_count_enable, sample_tick, baud_tick, current_state, use_parity_bit)
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begin
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if rising_edge(clk) then
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--sample counter
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if rx_enable = '1' or reset = '1' then
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period16_count_q <= period16_count_d;
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end if;
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--baud counter
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if period_count_enable = '1' or reset = '1' then
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period_count_q <= period_count_d;
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end if;
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if sample_tick = '1' then
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sample_reg_q <= sample_reg_d;
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rx_sampled_q <= rx_sampled_d;
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sample_reg_start_bit_q <= sample_reg_start_bit_d;
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end if;
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if baud_tick = '1' or (current_state = idle and sample_reg_start_bit_q = start_samples) or current_state = data_check or current_state = data_rdy then
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current_state <= next_state;
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end if;
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if baud_tick = '1' and current_state = data_bit0 then
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sampled_data(0) <= rx_sampled_q;
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end if;
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if baud_tick = '1' and current_state = data_bit1 then
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sampled_data(1) <= rx_sampled_q;
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end if;
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if baud_tick = '1' and current_state = data_bit2 then
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sampled_data(2) <= rx_sampled_q;
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end if;
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if baud_tick = '1' and current_state = data_bit3 then
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sampled_data(3) <= rx_sampled_q;
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end if;
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if baud_tick = '1' and current_state = data_bit4 then
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sampled_data(4) <= rx_sampled_q;
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end if;
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if baud_tick = '1' and current_state = data_bit5 then
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sampled_data(5) <= rx_sampled_q;
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end if;
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if baud_tick = '1' and current_state = data_bit6 then
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sampled_data(6) <= rx_sampled_q;
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end if;
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if baud_tick = '1' and current_state = data_bit7 then
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sampled_data(7) <= rx_sampled_q;
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end if;
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if baud_tick = '1' and current_state = stop_bit1 then
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sampled_data(8) <= rx_sampled_q;
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end if;
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if baud_tick = '1' and current_state = stop_bit2 then
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sampled_data(9) <= rx_sampled_q;
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end if;
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if current_state = data_check then
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data <= sampled_data(7 downto 0);
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end if;
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if baud_tick = '1' and use_parity_bit = '1' then
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xored_sampled_data_bit_q <= xored_sampled_data_bit_d;
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end if;
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end if;
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end process register_logic;
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end architecture behaviour;
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