| Line 22... |
Line 22... |
type ram_type is array (0 to 2**address_width-1) of std_logic_vector(7 downto 0);
|
type ram_type is array (0 to 2**address_width-1) of std_logic_vector(7 downto 0);
|
signal ram : ram_type;
|
signal ram : ram_type;
|
|
|
constant max_fifo_entries : std_logic_vector(address_width downto 0) := conv_std_logic_vector(2**address_width, address_width+1);
|
constant max_fifo_entries : std_logic_vector(address_width downto 0) := conv_std_logic_vector(2**address_width, address_width+1);
|
signal tx_entries_back_d : std_logic_vector(address_width downto 0);
|
signal tx_entries_back_d : std_logic_vector(address_width downto 0);
|
signal tx_entries_back_q : std_logic_vector(address_width downto 0) := max_fifo_entries ;
|
signal tx_entries_back_q : std_logic_vector(address_width downto 0);
|
signal tx_in_addr_d, tx_out_addr_d : std_logic_vector(address_width-1 downto 0);
|
signal tx_in_addr_d, tx_out_addr_d : std_logic_vector(address_width-1 downto 0);
|
signal tx_in_addr_q, tx_out_addr_q : std_logic_vector(address_width-1 downto 0) := (others => '0');
|
signal tx_in_addr_q, tx_out_addr_q : std_logic_vector(address_width-1 downto 0);
|
|
signal tx_in_addr_en, tx_out_addr_en, tx_entries_back_en : std_logic;
|
|
|
signal ram_we : std_logic;
|
signal ram_we : std_logic;
|
signal ram_address : std_logic_vector(address_width-1 downto 0) := (others => '0');
|
signal ram_address : std_logic_vector(address_width-1 downto 0);
|
signal tx_fifo_empty_i : std_logic := '1';
|
signal tx_fifo_empty_i : std_logic := '1';
|
signal tx_fifo_full_i : std_logic := '0';
|
signal tx_fifo_full_i : std_logic := '0';
|
|
|
signal tx_func_apply_data_i : std_logic;
|
signal tx_func_apply_data_i : std_logic;
|
|
|
|
|
begin
|
begin
|
--------------------
|
--------------------
|
-- Component used --
|
-- Component used --
|
--------------------
|
--------------------
|
|
|
| Line 52... |
Line 52... |
with ram_we select
|
with ram_we select
|
ram_address <= tx_in_addr_q when '1',
|
ram_address <= tx_in_addr_q when '1',
|
tx_out_addr_q when '0',
|
tx_out_addr_q when '0',
|
tx_out_addr_q when others;
|
tx_out_addr_q when others;
|
|
|
|
tx_in_addr_en <= reset or ram_we;
|
tx_in_addr_d <= (others => '0') when reset = '1' else
|
tx_in_addr_d <= (others => '0') when reset = '1' else
|
tx_in_addr_q + 1;-- when ram_we = '1' else --taken care of by the register enable
|
tx_in_addr_q + 1;-- when ram_we = '1' else --taken care of by the register enable
|
--tx_in_addr_q;
|
--tx_in_addr_q;
|
|
tx_out_addr_en <= reset or tx_func_apply_data_i;
|
tx_out_addr_d <= (others => '0') when reset = '1' else
|
tx_out_addr_d <= (others => '0') when reset = '1' else
|
tx_out_addr_q + 1;-- when tx_func_apply_data_i = '1' else
|
tx_out_addr_q + 1;-- when tx_func_apply_data_i = '1' else
|
--tx_out_addr_q;
|
--tx_out_addr_q;
|
|
|
tx_func_apply_data <= tx_func_apply_data_i;
|
tx_func_apply_data <= tx_func_apply_data_i;
|
| Line 72... |
Line 74... |
tx_fifo_full <= tx_fifo_full_i;
|
tx_fifo_full <= tx_fifo_full_i;
|
tx_fifo_full_i <= '0' when tx_entries_back_q /= conv_std_logic_vector(0, address_width+1) else
|
tx_fifo_full_i <= '0' when tx_entries_back_q /= conv_std_logic_vector(0, address_width+1) else
|
'1';
|
'1';
|
|
|
tx_fifo_entries_free <= conv_std_logic_vector(0,7-address_width) & tx_entries_back_q;
|
tx_fifo_entries_free <= conv_std_logic_vector(0,7-address_width) & tx_entries_back_q;
|
|
tx_entries_back_en <= reset or ram_we or tx_func_apply_data_i;
|
tx_entries_back_d <= max_fifo_entries when reset = '1' else
|
tx_entries_back_d <= max_fifo_entries when reset = '1' else
|
tx_entries_back_q - 1 when ram_we = '1' else
|
tx_entries_back_q - 1 when ram_we = '1' else
|
tx_entries_back_q + 1;-- when tx_func_apply_data_i = '1' else
|
tx_entries_back_q + 1;-- when tx_func_apply_data_i = '1' else
|
--tx_entries_back_q;
|
--tx_entries_back_q;
|
|
|
--------------------
|
--------------------
|
-- Register Logic --
|
-- Register Logic --
|
--------------------
|
--------------------
|
reg_control : process(clk, reset, ram_we, tx_func_apply_data_i, tx_data)
|
reg_control : process(clk, tx_entries_back_en, tx_out_addr_en, tx_in_addr_en, tx_entries_back_d, tx_out_addr_d, tx_in_addr_d)
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
if reset = '1' or ram_we = '1' or tx_func_apply_data_i = '1' then
|
if tx_entries_back_en = '1' then
|
tx_entries_back_q <= tx_entries_back_d;
|
tx_entries_back_q <= tx_entries_back_d;
|
end if;
|
end if;
|
|
|
if reset = '1' or tx_func_apply_data_i = '1' then
|
if tx_out_addr_en = '1' then
|
tx_out_addr_q <= tx_out_addr_d;
|
tx_out_addr_q <= tx_out_addr_d;
|
end if;
|
end if;
|
|
|
if reset = '1' or ram_we = '1' then
|
if tx_in_addr_en = '1' then
|
tx_in_addr_q <= tx_in_addr_d;
|
tx_in_addr_q <= tx_in_addr_d;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process reg_control;
|
end process reg_control;
|
|
|
