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//****************************************************//
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// This controller provides timing synchronization //
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// among all four modules (SC, KES, CSEE and FIFO //
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// Registers). It consists of 2 FSMs that operate on //
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// different clock phases. //
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// With these FSMs, it is possible for SC block to //
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// get new received word data, while CSEE is still //
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// correcting old data. It is no need to wait the //
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// CSEE block to correct old data completely. //
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// So, it can minimize throughput bottleneck //
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// to only in KES block. //
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//****************************************************//
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No newline at end of file
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No newline at end of file
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module MainControl(start, reset, clock1, clock2, finish_kes,
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errdetect, rootcntr, lambda_degree, active_sc,
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active_kes, active_csee, evalsynd, holdsynd,
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errfound, decode_fail, ready, dataoutstart,
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dataoutend, shift_fifo, hold_fifo, en_infifo,
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en_outfifo, lastdataout, evalerror);
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input start, reset;
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input clock1, clock2;
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input errdetect, finish_kes;
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input [2:0] rootcntr, lambda_degree;
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output active_sc, active_kes, active_csee, ready;
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output evalsynd, holdsynd, errfound, decode_fail;
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output dataoutstart, dataoutend;
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output shift_fifo, hold_fifo, en_infifo, en_outfifo;
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output lastdataout, evalerror;
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reg active_sc, active_kes, active_csee;
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reg ready, decode_fail, evalsynd, holdsynd, errfound;
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reg shift_fifo, hold_fifo, en_infifo, en_outfifo;
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reg encntdataout, encntdatain;
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reg [4:0] cntdatain, cntdataout;
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reg dataoutstart, dataoutend;
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reg datainfinish;
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wire lastdataout;
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parameter [3:0] st1_0=0, st1_1=1, st1_2=2, st1_3=3, st1_4=4, st1_5=5,
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st1_6=6, st1_7=7, st1_8=8, st1_9=9, st1_10=10,
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st1_11=11, st1_12=12, st1_13=13, st1_14=14;
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reg [3:0] state1, nxt_state1;
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parameter [3:0] st2_0=0, st2_1=1, st2_2=2, st2_3=3, st2_4=4, st2_5=5,
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st2_6=6, st2_7=7, st2_8=8, st2_9=9, st2_10=10,
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st2_11=11;
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reg [3:0] state2, nxt_state2;
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//***************************************************//
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// FSM 1 //
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//***************************************************//
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always@(posedge clock1 or negedge reset)
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begin
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if(~reset)
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state1 = st1_0;
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else
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state1 = nxt_state1;
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end
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always@(state1 or start or rootcntr or lambda_degree or errdetect
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or datainfinish or finish_kes or dataoutend)
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begin
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case(state1)
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st1_0 : begin
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if(start)
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nxt_state1 = st1_1;
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else
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nxt_state1 = st1_0;
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end
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st1_1 : nxt_state1 = st1_2;
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st1_2 : begin
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if(datainfinish)
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nxt_state1 = st1_3;
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else
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nxt_state1 = st1_2;
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end
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st1_3 : begin
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if(errdetect)
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nxt_state1 = st1_4;
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else
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nxt_state1 = st1_12;
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end
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st1_4 : nxt_state1 = st1_5;
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st1_5 : begin
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if(finish_kes)
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nxt_state1 = st1_6;
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else
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nxt_state1 = st1_5;
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end
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st1_6 : nxt_state1 = st1_7;
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st1_7 : begin
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if((~start)&&(~dataoutend))
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nxt_state1 = st1_7;
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else if(dataoutend)
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begin
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if(lambda_degree == rootcntr)
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nxt_state1 = st1_0;
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else
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nxt_state1 = st1_10;
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end
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else
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nxt_state1 = st1_8;
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end
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st1_8 : begin
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if(dataoutend)
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begin
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if(lambda_degree == rootcntr)
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nxt_state1 = st1_2;
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else
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nxt_state1 = st1_11;
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end
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else
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nxt_state1 = st1_9;
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end
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st1_9 : begin
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if(dataoutend)
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begin
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if(lambda_degree == rootcntr)
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nxt_state1 = st1_2;
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else
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nxt_state1 = st1_11;
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end
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else
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nxt_state1 = st1_9;
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end
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st1_10: begin
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if(start)
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nxt_state1 = st1_1;
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else
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nxt_state1 = st1_0;
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end
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st1_11: begin
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if(datainfinish)
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nxt_state1 = st1_3;
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else
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nxt_state1 = st1_2;
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end
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st1_12: begin
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if((~start)&&(~dataoutend))
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nxt_state1 = st1_12;
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else if(dataoutend)
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nxt_state1 = st1_0;
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else
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nxt_state1 = st1_13;
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end
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st1_13: begin
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if(dataoutend)
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nxt_state1 = st1_2;
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else
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nxt_state1 = st1_14;
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end
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st1_14: begin
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if(dataoutend)
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nxt_state1 = st1_2;
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else
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nxt_state1 = st1_14;
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end
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default: nxt_state1 = st1_0;
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endcase
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end
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// Output logic of FSM1 //
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always@(state1)
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begin
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case(state1)
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st1_0 :begin
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ready = 1;
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active_sc = 0;
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active_kes = 0;
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active_csee = 0;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 0;
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en_outfifo = 0;
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end
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st1_1 :begin
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ready = 1;
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active_sc = 1;
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active_kes = 0;
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active_csee = 0;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 0;
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en_outfifo = 0;
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end
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st1_2 :begin
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ready = 1;
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active_sc = 0;
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active_kes = 0;
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active_csee = 0;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 0;
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en_outfifo = 0;
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end
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st1_3 :begin
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ready = 0;
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active_sc = 0;
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active_kes = 0;
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active_csee = 0;
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evalsynd = 1;
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errfound = 0;
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decode_fail = 0;
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en_outfifo = 0;
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end
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st1_4 :begin
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ready = 0;
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active_sc = 0;
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active_kes = 1;
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active_csee = 0;
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evalsynd = 0;
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errfound = 1;
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decode_fail = 0;
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en_outfifo = 0;
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end
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st1_5 :begin
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ready = 0;
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active_sc = 0;
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active_kes = 1;
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active_csee = 0;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 0;
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en_outfifo = 0;
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end
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st1_6 :begin
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ready = 0;
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active_sc = 0;
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active_kes = 1;
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active_csee = 1;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 0;
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en_outfifo = 0;
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end
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st1_7 :begin
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ready = 1;
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active_sc = 0;
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active_kes = 1;
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active_csee = 0;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 0;
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en_outfifo = 1;
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end
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st1_8 :begin
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ready = 1;
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active_sc = 1;
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active_kes = 1;
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active_csee = 0;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 0;
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en_outfifo = 1;
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end
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st1_9 :begin
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ready = 1;
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active_sc = 0;
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active_kes = 1;
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active_csee = 0;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 0;
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en_outfifo = 1;
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end
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st1_10:begin
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ready = 1;
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active_sc = 0;
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active_kes = 0;
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active_csee = 0;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 1;
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en_outfifo = 0;
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end
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st1_11:begin
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ready = 1;
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active_sc = 0;
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active_kes = 0;
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active_csee = 0;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 1;
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en_outfifo = 0;
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end
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st1_12:begin
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ready = 1;
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active_sc = 0;
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active_kes = 0;
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active_csee = 0;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 0;
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en_outfifo = 1;
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end
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st1_13:begin
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ready = 1;
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active_sc = 1;
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active_kes = 0;
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active_csee = 0;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 0;
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en_outfifo = 1;
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end
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st1_14:begin
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ready = 1;
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active_sc = 0;
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active_kes = 0;
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active_csee = 0;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 0;
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en_outfifo = 1;
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end
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default:begin
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ready = 1;
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active_sc = 0;
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active_kes = 0;
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active_csee = 0;
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evalsynd = 0;
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errfound = 0;
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decode_fail = 0;
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en_outfifo = 0;
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end
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endcase
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end
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//****************************************//
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// FSM 2 //
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//****************************************//
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always@(posedge clock2 or negedge reset)
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begin
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if(~reset)
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state2 = st2_0;
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else
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state2 = nxt_state2;
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end
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always@(state2 or active_sc or cntdatain or lastdataout or en_outfifo)
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begin
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case(state2)
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st2_0 : begin
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if(active_sc)
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nxt_state2 = st2_1;
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else
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nxt_state2 = st2_0;
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end
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st2_1 : begin
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if(cntdatain == 5'b11110)
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nxt_state2 = st2_2;
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else
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nxt_state2 = st2_1;
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end
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st2_2 : nxt_state2 = st2_3;
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st2_3 : begin
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if(en_outfifo)
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nxt_state2 = st2_4;
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else
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nxt_state2 = st2_3;
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end
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st2_4 : begin
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if(active_sc)
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nxt_state2 = st2_8;
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else
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nxt_state2 = st2_5;
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end
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st2_5 : begin
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if(active_sc)
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nxt_state2 = st2_9;
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else
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nxt_state2 = st2_6;
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end
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st2_6 : begin
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if(active_sc)
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nxt_state2 = st2_9;
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else if((lastdataout) && (~active_sc))
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nxt_state2 = st2_7;
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else
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nxt_state2 = st2_6;
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end
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st2_7 : begin
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if(active_sc)
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nxt_state2 = st2_1;
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else
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nxt_state2 = st2_0;
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end
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st2_8 : nxt_state2 = st2_9;
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st2_9 : begin
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if((lastdataout) && (cntdatain==5'b11110))
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nxt_state2 = st2_10;
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else if(lastdataout)
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nxt_state2 = st2_11;
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else
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nxt_state2 = st2_9;
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end
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st2_10: nxt_state2 = st2_3;
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st2_11: begin
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if(cntdatain==5'b11110)
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nxt_state2 = st2_2;
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else
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nxt_state2 = st2_1;
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end
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default: nxt_state2 = st2_0;
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endcase
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end
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// Output logic of FSM 2 //
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always@(state2)
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begin
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case(state2)
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st2_0 : begin
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dataoutstart = 0;
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dataoutend = 0;
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shift_fifo = 0;
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hold_fifo = 0;
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en_infifo = 0;
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encntdatain = 0;
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encntdataout = 0;
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holdsynd = 0;
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datainfinish = 0;
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end
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st2_1 : begin
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dataoutstart = 0;
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dataoutend = 0;
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shift_fifo = 1;
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hold_fifo = 0;
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en_infifo = 1;
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encntdatain = 1;
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encntdataout = 0;
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holdsynd = 0;
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datainfinish = 0;
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end
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st2_2 : begin
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dataoutstart = 0;
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dataoutend = 0;
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shift_fifo = 1;
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hold_fifo = 0;
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en_infifo = 1;
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encntdatain = 0;
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encntdataout = 0;
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holdsynd = 0;
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datainfinish = 1;
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end
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st2_3 : begin
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dataoutstart = 0;
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dataoutend = 0;
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shift_fifo = 0;
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hold_fifo = 1;
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en_infifo = 0;
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encntdatain = 0;
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encntdataout = 0;
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holdsynd = 1;
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datainfinish = 0;
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end
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st2_4 : begin
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dataoutstart = 0;
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dataoutend = 0;
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shift_fifo = 0;
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hold_fifo = 1;
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en_infifo = 0;
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encntdatain = 0;
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encntdataout = 1;
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holdsynd = 0;
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datainfinish = 0;
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end
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st2_5 : begin
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dataoutstart = 1;
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dataoutend = 0;
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shift_fifo = 1;
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hold_fifo = 0;
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en_infifo = 0;
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encntdatain = 0;
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encntdataout = 1;
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holdsynd = 0;
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datainfinish = 0;
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end
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st2_6 : begin
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dataoutstart = 0;
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dataoutend = 0;
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shift_fifo = 1;
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hold_fifo = 0;
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en_infifo = 0;
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encntdatain = 0;
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encntdataout = 1;
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holdsynd = 0;
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datainfinish = 0;
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end
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st2_7 : begin
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dataoutstart = 0;
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dataoutend = 1;
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shift_fifo = 0;
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hold_fifo = 0;
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en_infifo = 0;
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encntdatain = 0;
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encntdataout = 0;
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holdsynd = 0;
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datainfinish = 0;
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end
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st2_8 : begin
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dataoutstart = 1;
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dataoutend = 0;
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shift_fifo = 1;
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hold_fifo = 0;
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en_infifo = 1;
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encntdatain = 1;
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encntdataout = 1;
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holdsynd = 0;
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datainfinish = 0;
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end
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st2_9 : begin
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dataoutstart = 0;
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dataoutend = 0;
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shift_fifo = 1;
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hold_fifo = 0;
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en_infifo = 1;
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encntdatain = 1;
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encntdataout = 1;
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holdsynd = 0;
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datainfinish = 0;
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end
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st2_10: begin
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dataoutstart = 0;
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dataoutend = 1;
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shift_fifo = 1;
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hold_fifo = 0;
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en_infifo = 1;
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encntdatain = 0;
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encntdataout = 0;
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holdsynd = 0;
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datainfinish = 1;
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end
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st2_11: begin
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dataoutstart = 0;
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dataoutend = 1;
|
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shift_fifo = 1;
|
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hold_fifo = 0;
|
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en_infifo = 1;
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encntdatain = 1;
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encntdataout = 0;
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holdsynd = 0;
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datainfinish = 0;
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end
|
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default: begin
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dataoutstart = 0;
|
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dataoutend = 0;
|
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shift_fifo = 0;
|
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hold_fifo = 0;
|
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en_infifo = 0;
|
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encntdatain = 0;
|
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encntdataout = 0;
|
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holdsynd = 0;
|
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datainfinish = 0;
|
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end
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endcase
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end
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//*********************//
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// Counter for dataout //
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always@(posedge clock1)
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begin
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if(encntdataout)
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cntdataout = cntdataout + 1;
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else
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cntdataout = 5'b0;
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end
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// Counter for datain //
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|
always@(posedge clock1)
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|
begin
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|
if(encntdatain)
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|
cntdatain = cntdatain + 1;
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else
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|
cntdatain = 5'b0;
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end
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// lastdataout is 1 if cntdataout = 5'b11111 //
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assign lastdataout = cntdataout[4] & (cntdataout[3]&cntdataout[2]) &
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(cntdataout[1]&cntdataout[0]);
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|
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assign evalerror = encntdataout;
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|
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endmodule
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