| Line 40... |
Line 40... |
component rsa_top
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component rsa_top
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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valid_in : in std_logic;
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valid_in : in std_logic;
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start_in : in std_logic;
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x : in std_logic_vector(15 downto 0);
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x : in std_logic_vector(15 downto 0);
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y : in std_logic_vector(15 downto 0);
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y : in std_logic_vector(15 downto 0);
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m : in std_logic_vector(15 downto 0);
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m : in std_logic_vector(15 downto 0);
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r_c : in std_logic_vector(15 downto 0);
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r_c : in std_logic_vector(15 downto 0);
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n_c : in std_logic_vector(15 downto 0);
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s : out std_logic_vector(15 downto 0);
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s : out std_logic_vector(15 downto 0);
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valid_out : out std_logic;
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valid_out : out std_logic;
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bit_size : in std_logic_vector(15 downto 0)
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bit_size : in std_logic_vector(15 downto 0)
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);
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);
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end component;
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end component;
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| Line 56... |
Line 56... |
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--Inputs
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--Inputs
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal reset : std_logic := '0';
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signal reset : std_logic := '0';
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signal valid_in : std_logic := '0';
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signal valid_in : std_logic := '0';
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signal start_in : std_logic;
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signal x : std_logic_vector(15 downto 0) := (others => '0');
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signal x : std_logic_vector(15 downto 0) := (others => '0');
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signal y : std_logic_vector(15 downto 0) := (others => '0');
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signal y : std_logic_vector(15 downto 0) := (others => '0');
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signal m : std_logic_vector(15 downto 0) := (others => '0');
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signal m : std_logic_vector(15 downto 0) := (others => '0');
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signal r_c : std_logic_vector(15 downto 0) := (others => '0');
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signal r_c : std_logic_vector(15 downto 0) := (others => '0');
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signal n_c : std_logic_vector(15 downto 0) := (others => '0');
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signal n_c : std_logic_vector(15 downto 0) := (others => '0');
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| Line 76... |
Line 77... |
-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut : rsa_top port map (
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uut : rsa_top port map (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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valid_in => valid_in,
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valid_in => valid_in,
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start_in => start_in,
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x => x,
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x => x,
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y => y,
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y => y,
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m => m,
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m => m,
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r_c => r_c,
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r_c => r_c,
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n_c => n_c,
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s => s,
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s => s,
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valid_out => valid_out,
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valid_out => valid_out,
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bit_size => bit_size
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bit_size => bit_size
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);
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);
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|
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| Line 99... |
Line 100... |
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-- Stimulus process
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-- Stimulus process
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stim_proc : process
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stim_proc : process
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begin
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begin
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start_in <= '0';
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valid_in <= '0';
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valid_in <= '0';
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-- hold reset state for 100ms.
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-- hold reset state for 100ms.
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reset <= '1';
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reset <= '1';
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wait for 10ns;
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wait for 10ns;
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reset <= '0';
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reset <= '0';
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wait for clk_period*10;
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wait for clk_period*10;
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|
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-- insert stimulus here
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-- insert stimulus here
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|
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--n_c and valid signal and the r_c constant are also required
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--n_c and valid signal and the r_c constant are also required
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n_c <= x"738f";
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--n_c <= x"738f";
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valid_in <= '1';
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m <= x"b491";
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--Start_in to begin n_c calculation
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start_in <= '1';
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wait for clk_period;
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start_in <= '0';
|
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wait for clk_period*6;
|
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--Start data flow
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x <= x"f3ad";
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x <= x"f3ad";
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y <= x"42b1";
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y <= x"42b1";
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m <= x"b491";
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m <= x"b491";
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r_c <= x"f579";
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r_c <= x"f579";
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valid_in <= '1';
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wait for clk_period;
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wait for clk_period;
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x <= x"8e40";
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x <= x"8e40";
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y <= x"1ad3";
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y <= x"1ad3";
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m <= x"1417";
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m <= x"1417";
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r_c <= x"6ee9";
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r_c <= x"6ee9";
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| Line 437... |
Line 446... |
valid_in <= '0';
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valid_in <= '0';
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|
|
wait;
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wait;
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end process;
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end process;
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|
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END;
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end;
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No newline at end of file
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