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[/] [rsa_512/] [trunk/] [rtl/] [rsa_top.vhd] - Diff between revs 3 and 9

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Rev 3 Rev 9
Line 34... Line 34...
entity rsa_top is
entity rsa_top is
  port(
  port(
    clk       : in  std_logic;
    clk       : in  std_logic;
    reset     : in  std_logic;
    reset     : in  std_logic;
    valid_in  : in  std_logic;
    valid_in  : in  std_logic;
 
    start_in  : in  std_logic;
    x         : in  std_logic_vector(15 downto 0);  -- estos 3 son x^y mod m
    x         : in  std_logic_vector(15 downto 0);  -- estos 3 son x^y mod m
    y         : in  std_logic_vector(15 downto 0);
    y         : in  std_logic_vector(15 downto 0);
    m         : in  std_logic_vector(15 downto 0);
    m         : in  std_logic_vector(15 downto 0);
    r_c       : in  std_logic_vector(15 downto 0);  --constante de montgomery r^2 mod m
    r_c       : in  std_logic_vector(15 downto 0);  --constante de montgomery r^2 mod m
    n_c       : in  std_logic_vector(15 downto 0);  --constante necesaria en la multiplicacion
 
    s         : out std_logic_vector( 15 downto 0);
    s         : out std_logic_vector( 15 downto 0);
    valid_out : out std_logic;
    valid_out : out std_logic;
    bit_size  : in  std_logic_vector(15 downto 0)  --tamano bit del exponente y (log2(y))
    bit_size  : in  std_logic_vector(15 downto 0)  --tamano bit del exponente y (log2(y))
    );
    );
end rsa_top;
end rsa_top;
 
 
architecture Behavioral of rsa_top is
architecture Behavioral of rsa_top is
 
 
 
  component n_c_core
 
    port (clk   : in  std_logic;
 
          m_lsw : in  std_logic_vector(15 downto 0);
 
          ce    : in  std_logic;
 
          n_c   : out std_logic_vector(15 downto 0);
 
          done  : out std_logic
 
          );
 
  end component;
 
 
--Multiplicador de Montgomery que sera instanciado 2 veces
--Multiplicador de Montgomery que sera instanciado 2 veces
  component montgomery_mult is
  component montgomery_mult
                              port(
                              port(
                                clk       : in  std_logic;
                                clk       : in  std_logic;
                                reset     : in  std_logic;
                                reset     : in  std_logic;
                                valid_in  : in  std_logic;
                                valid_in  : in  std_logic;
                                a         : in  std_logic_vector(15 downto 0);
                                a         : in  std_logic_vector(15 downto 0);
Line 108... Line 116...
  signal count_input, next_count_input, bit_counter, next_bit_counter : std_logic_vector(15 downto 0);
  signal count_input, next_count_input, bit_counter, next_bit_counter : std_logic_vector(15 downto 0);
 
 
  signal bsize_reg, next_bsize_reg : std_logic_vector (15 downto 0);
  signal bsize_reg, next_bsize_reg : std_logic_vector (15 downto 0);
  signal write_b_n                 : std_logic_vector(0 downto 0);
  signal write_b_n                 : std_logic_vector(0 downto 0);
 
 
 
  signal n_c_o    : std_logic_vector(15 downto 0);
 
  signal n_c      : std_logic_vector(15 downto 0);
 
  signal n_c_load : std_logic;
 
 
begin
begin
 
 
 
  n_c1 : n_c_core
 
    port map (
 
      clk   => clk,
 
      m_lsw => m,
 
      ce    => start_in,
 
      n_c   => n_c_o,
 
      done  => n_c_load
 
      );
 
 
 
 
  mon_1 : montgomery_mult port map(
  mon_1 : montgomery_mult port map(
    clk       => clk,
    clk       => clk,
    reset     => reset,
    reset     => reset,
    valid_in  => valid_in_mon_1,
    valid_in  => valid_in_mon_1,
Line 178... Line 199...
        count_input <= (others => '0');
        count_input <= (others => '0');
        addr_exp    <= (others => '0');
        addr_exp    <= (others => '0');
        addr_n      <= (others => '0');
        addr_n      <= (others => '0');
        bit_counter <= (others => '0');
        bit_counter <= (others => '0');
        bsize_reg   <= (others => '0');
        bsize_reg   <= (others => '0');
 
        n_c         <= (others => '0');
 
 
      else
      else
 
        if(n_c_load = '1') then
 
          n_c       <= n_c_o;
 
        end if;
        state       <= next_state;
        state       <= next_state;
        n_c_reg     <= next_n_c_reg;
        n_c_reg     <= next_n_c_reg;
        w_numb      <= next_w_numb;
        w_numb      <= next_w_numb;
        count_input <= next_count_input;
        count_input <= next_count_input;
        addr_exp    <= next_addr_exp;
        addr_exp    <= next_addr_exp;

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