| Line 34... |
Line 34... |
entity rsa_top is
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entity rsa_top is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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valid_in : in std_logic;
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valid_in : in std_logic;
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start_in : in std_logic;
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x : in std_logic_vector(15 downto 0); -- estos 3 son x^y mod m
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x : in std_logic_vector(15 downto 0); -- estos 3 son x^y mod m
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y : in std_logic_vector(15 downto 0);
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y : in std_logic_vector(15 downto 0);
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m : in std_logic_vector(15 downto 0);
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m : in std_logic_vector(15 downto 0);
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r_c : in std_logic_vector(15 downto 0); --constante de montgomery r^2 mod m
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r_c : in std_logic_vector(15 downto 0); --constante de montgomery r^2 mod m
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n_c : in std_logic_vector(15 downto 0); --constante necesaria en la multiplicacion
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s : out std_logic_vector( 15 downto 0);
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s : out std_logic_vector( 15 downto 0);
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valid_out : out std_logic;
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valid_out : out std_logic;
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bit_size : in std_logic_vector(15 downto 0) --tamano bit del exponente y (log2(y))
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bit_size : in std_logic_vector(15 downto 0) --tamano bit del exponente y (log2(y))
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);
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);
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end rsa_top;
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end rsa_top;
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architecture Behavioral of rsa_top is
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architecture Behavioral of rsa_top is
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component n_c_core
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port (clk : in std_logic;
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m_lsw : in std_logic_vector(15 downto 0);
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ce : in std_logic;
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n_c : out std_logic_vector(15 downto 0);
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done : out std_logic
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);
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end component;
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--Multiplicador de Montgomery que sera instanciado 2 veces
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--Multiplicador de Montgomery que sera instanciado 2 veces
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component montgomery_mult is
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component montgomery_mult
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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valid_in : in std_logic;
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valid_in : in std_logic;
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a : in std_logic_vector(15 downto 0);
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a : in std_logic_vector(15 downto 0);
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| Line 108... |
Line 116... |
signal count_input, next_count_input, bit_counter, next_bit_counter : std_logic_vector(15 downto 0);
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signal count_input, next_count_input, bit_counter, next_bit_counter : std_logic_vector(15 downto 0);
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signal bsize_reg, next_bsize_reg : std_logic_vector (15 downto 0);
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signal bsize_reg, next_bsize_reg : std_logic_vector (15 downto 0);
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signal write_b_n : std_logic_vector(0 downto 0);
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signal write_b_n : std_logic_vector(0 downto 0);
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signal n_c_o : std_logic_vector(15 downto 0);
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signal n_c : std_logic_vector(15 downto 0);
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signal n_c_load : std_logic;
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begin
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begin
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n_c1 : n_c_core
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port map (
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clk => clk,
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m_lsw => m,
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ce => start_in,
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n_c => n_c_o,
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done => n_c_load
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);
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mon_1 : montgomery_mult port map(
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mon_1 : montgomery_mult port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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valid_in => valid_in_mon_1,
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valid_in => valid_in_mon_1,
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| Line 178... |
Line 199... |
count_input <= (others => '0');
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count_input <= (others => '0');
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addr_exp <= (others => '0');
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addr_exp <= (others => '0');
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addr_n <= (others => '0');
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addr_n <= (others => '0');
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bit_counter <= (others => '0');
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bit_counter <= (others => '0');
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bsize_reg <= (others => '0');
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bsize_reg <= (others => '0');
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n_c <= (others => '0');
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else
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else
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if(n_c_load = '1') then
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n_c <= n_c_o;
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end if;
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state <= next_state;
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state <= next_state;
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n_c_reg <= next_n_c_reg;
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n_c_reg <= next_n_c_reg;
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w_numb <= next_w_numb;
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w_numb <= next_w_numb;
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count_input <= next_count_input;
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count_input <= next_count_input;
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addr_exp <= next_addr_exp;
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addr_exp <= next_addr_exp;
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