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[/] [rtc/] [trunk/] [rtl/] [verilog/] [rtc_top.v] - Diff between revs 15 and 17

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Rev 15 Rev 17
Line 44... Line 44...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.1  2001/09/18 22:55:39  lampret
 
// Changed rtc into rtc_top. Changed defines.v into rtc_defines.v. Fixed a bug with two defines for alarms.
 
//
// Revision 1.2  2001/08/22 10:58:27  lampret
// Revision 1.2  2001/08/22 10:58:27  lampret
// Changed synthesis translate_ to synopsys translate.
// Changed synthesis translate_ to synopsys translate.
//
//
// Revision 1.1  2001/08/21 12:53:11  lampret
// Revision 1.1  2001/08/21 12:53:11  lampret
// Changed directory structure, uniquified defines and changed design's port names.
// Changed directory structure, uniquified defines and changed design's port names.
Line 227... Line 230...
// b) sel_i evaluation is enabled and one of the sel_i inputs is zero
// b) sel_i evaluation is enabled and one of the sel_i inputs is zero
//
//
assign wb_ack_o = wb_cyc_i & wb_stb_i & !wb_err_o;
assign wb_ack_o = wb_cyc_i & wb_stb_i & !wb_err_o;
`ifdef RTC_FULL_DECODE
`ifdef RTC_FULL_DECODE
`ifdef RTC_STRICT_32BIT_ACCESS
`ifdef RTC_STRICT_32BIT_ACCESS
assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding | (wb_sel_i != 4'b1111);
assign wb_err_o = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
`else
`else
assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding;
assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding;
`endif
`endif
`else
`else
`ifdef RTC_STRICT_32BIT_ACCESS
`ifdef RTC_STRICT_32BIT_ACCESS
assign wb_err_o = (wb_sel_i != 4'b1111);
assign wb_err_o = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
`else
`else
assign wb_err_o = 1'b0;
assign wb_err_o = 1'b0;
`endif
`endif
`endif
`endif
 
 

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