| Line 66... |
Line 66... |
You should have received a copy of the GNU General Public License along
|
You should have received a copy of the GNU General Public License along
|
with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a
|
with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a
|
copy.
|
copy.
|
\end{license}
|
\end{license}
|
\begin{revisionhistory}
|
\begin{revisionhistory}
|
|
0.2 & 7/11/2015 & Gisselquist & Date interface added\\\hline
|
0.1 & 5/25/2015 & Gisselquist & First Draft \\\hline
|
0.1 & 5/25/2015 & Gisselquist & First Draft \\\hline
|
\end{revisionhistory}
|
\end{revisionhistory}
|
% Revision History
|
% Revision History
|
% Table of Contents, named Contents
|
% Table of Contents, named Contents
|
\tableofcontents
|
\tableofcontents
|
| Line 78... |
Line 79... |
\begin{preface}
|
\begin{preface}
|
Every FPGA project needs to start with a very simple core. Then, working
|
Every FPGA project needs to start with a very simple core. Then, working
|
from simplicity, more and more complex cores can be built until an eventual
|
from simplicity, more and more complex cores can be built until an eventual
|
application comes from all the tiny details.
|
application comes from all the tiny details.
|
|
|
This real time clock is one such simple core. All of the pieces to this
|
This real time clock began with one such simple core. All of the pieces to
|
clock are simple. Nothing is inherently complex. However, placing this
|
this clock are simple. Nothing is inherently complex. However, placing this
|
clock into a larger FPGA structure requires a Wishbone bus, and being able
|
clock into a larger FPGA structure requires a Wishbone bus, and being able
|
to command and control an FPGA over a wishbone bus is an achievement in
|
to command and control an FPGA over a wishbone bus is an achievement in
|
itself. Further, the clock produces seven segment display output values
|
itself. Further, the clock produces seven segment display output values
|
and LED output values. These are also simple outputs, but still take a lot
|
and LED output values. These are also simple outputs, but still take a lot
|
of work to complete. Finally, this clock will strobe an interrupt line.
|
of work to complete. Finally, this clock will strobe an interrupt line.
|
| Line 95... |
Line 96... |
\chapter{Introduction}
|
\chapter{Introduction}
|
\pagenumbering{arabic}
|
\pagenumbering{arabic}
|
\setcounter{page}{1}
|
\setcounter{page}{1}
|
|
|
This Real--Time Clock implements a twenty four hour clock, count-down timer,
|
This Real--Time Clock implements a twenty four hour clock, count-down timer,
|
stopwatch
|
stopwatch and alarm. It is designed to be configurable to adjust to whatever
|
and alarm. It is designed to be configurable to adjust to whatever clock
|
clock speed the underlying architecture is running on, so with only minor
|
speed the underlying architecture is running on, so with only minor changes
|
changes should run on any fundamental clock rate from about 66~kHz on up to
|
should run on any fundamental clock rate from about 66~kHz on up to
|
|
250~TeraHertz with varying levels of accuracy along the way.
|
250~TeraHertz with varying levels of accuracy along the way.
|
|
|
This clock offers a fairly full feature set of capability: time, alarms,
|
Distributed with this clock is a similar Real--Time Date module. This
|
a countdown timer and a stopwatch, all features which are available from the
|
second module can track the day, month, and year while properly accounting
|
wishbone bus.
|
for varying days in each month and leap years, when they happen.
|
|
|
|
Together, the clock and date module offer a fairly full feature set of
|
|
capability: date, time, alarms, a countdown timer and a stopwatch, all
|
|
features which are available from the wishbone bus.
|
|
|
Other interfaces exist as well.
|
Other interfaces exist as well.
|
|
|
Should you wish to investigate your clock's
|
Should you wish to investigate your clock's stability or try to guarantee
|
stability or try to guarantee it's fine precision accuracy, it is possible to
|
its fine precision accuracy, it is possible to provide a time hack pulse to
|
provide a time hack pulse to the clock and subsequently read what all of the
|
the clock and subsequently read what all of the internal registers were set
|
internal registers were set to at that time.
|
to at that time.
|
|
|
When either the count--down timer reaches zero or the clock reaches the alarm
|
When either the count--down timer reaches zero or the clock reaches the alarm
|
time (if set), the clock module will produce an impulse which can be used
|
time (if set), the clock module will produce an impulse which can be used as
|
as an interrupt trigger.
|
an interrupt trigger.
|
|
|
This clock will also provide outputs sufficient to drive an external seven
|
This clock will also provide outputs sufficient to drive an external seven
|
segment display driver and 16 LED's.
|
segment display driver and 16 LED's.
|
|
|
Future enhancements may allow for button control and fine precision clock
|
Future enhancements may allow for button control and fine precision clock
|
| Line 140... |
Line 144... |
|
|
\chapter{Architecture}\label{chap:arch}
|
\chapter{Architecture}\label{chap:arch}
|
|
|
Central to this real time clock architecture is a 48~bit sub--second register.
|
Central to this real time clock architecture is a 48~bit sub--second register.
|
This register is incremented every clock by a user defined 32~bit value,
|
This register is incremented every clock by a user defined 32~bit value,
|
{\tt CKSPEED}.
|
{\tt CKSPEED}. When the register turns over at the end of each second, a
|
When the register turns over at the end of each second, a second has taken
|
second has taken place and all of the various clock (and date) registers are
|
place and all of the various clock registers are adjusted.
|
adjusted.
|
|
|
Well, not quite but almost. The 48~bit register is actually split into a
|
Well, not quite but almost. The 48~bit register is actually split into a
|
lower 40~bit register that is common to all clock components, as well as
|
lower 40~bit register that is common to all clock components, as well as
|
separate eight bit upper registers for the clock, timer, and stopwatch. In
|
separate eight bit upper registers for the clock, timer, and stopwatch. In
|
this fashion, these separate components can have different definitions for
|
this fashion, these separate components can have different definitions for
|
| Line 222... |
Line 226... |
the current time within the device.
|
the current time within the device.
|
|
|
It is the users responsibility to read the time hack registers before a
|
It is the users responsibility to read the time hack registers before a
|
subsequent time hack pulse sets them to new values.
|
subsequent time hack pulse sets them to new values.
|
|
|
|
\section{Date}
|
|
The Real--Time Date module is really a separate module from the Real--Time
|
|
Clock module, but that doesn't prevent it from working just like the others.
|
|
To set the date, just write the new date value to the address of the date.
|
|
Further, as with the clock time, setting any particular field of the date to
|
|
all ones, such as setting the month to {\tt 8'hff}, will cause that portion of
|
|
the date to retain it's current value. In this way, one part of the date
|
|
may be set and not others.
|
|
|
\chapter{Registers}\label{chap:regs}
|
\chapter{Registers}\label{chap:regs}
|
This RTC clock module supports eight registers, as listed in
|
This RTC clock module supports eight registers, as listed in
|
Tbl.~\ref{tbl:reglist}. Of these eight, the first four have been so placed
|
Tbl.~\ref{tbl:reglist}. Of these eight, the first four have been so placed
|
as to be the more routine or user used registers, while the latter four are
|
as to be the more routine or user used registers, while the latter four are
|
more lower level.
|
more lower level.
|
| Line 242... |
Line 255... |
HACKCNTLO&7 & 32 & R & Wall clock time.\\\hline
|
HACKCNTLO&7 & 32 & R & Wall clock time.\\\hline
|
\end{reglist}\caption{List of Registers}\label{tbl:reglist}
|
\end{reglist}\caption{List of Registers}\label{tbl:reglist}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
Each register will be discussed in detail in this chapter.
|
Each register will be discussed in detail in this chapter.
|
|
|
|
The Date module supports an additional register, listed in
|
|
Tbl.~\ref{tbl:datereg}.
|
|
\begin{table}[htbp]
|
|
\begin{center}
|
|
\begin{reglist}
|
|
DATE & 0 & 32 & R/W & Calendar date register\\\hline
|
|
\end{reglist}\caption{Date Register}\label{tbl:datereg}
|
|
\end{center}\end{table}
|
|
This register will be discussed after we discuss the time registers.
|
|
|
\section{Clock Time Register}
|
\section{Clock Time Register}
|
The various bit fields associated with the current time may be found in
|
The various bit fields associated with the current time may be found in
|
the {\tt CLOCK} register, shown in Tbl.~\ref{tbl:clockreg}.
|
the {\tt CLOCK} register, shown in Tbl.~\ref{tbl:clockreg}.
|
\begin{table}[htbp]\begin{center}
|
\begin{table}[htbp]\begin{center}
|
\begin{bitlist}
|
\begin{bitlist}
|
| Line 411... |
Line 434... |
At present, this functionality isn't yet truly fully featured. Once fully
|
At present, this functionality isn't yet truly fully featured. Once fully
|
featured, there will (should) be a mechanism for adjusting this counter based
|
featured, there will (should) be a mechanism for adjusting this counter based
|
upon information gleaned from the hack time. Implementation details have
|
upon information gleaned from the hack time. Implementation details have
|
to date prevented this portion of the design from being implemented.
|
to date prevented this portion of the design from being implemented.
|
|
|
|
\section{Date Register}
|
|
The year, month, and day of month fields may all be found within the
|
|
{\tt DATE} register of the Real--Time Date module, shown in
|
|
Tbl.~\ref{tbl:datebits}.
|
|
\begin{table}[htbp]\begin{center}
|
|
\begin{bitlist}
|
|
30--31 & R & Always return zero.\\\hline
|
|
16--29 & R/W & Four digit BCD year\\\hline
|
|
13--15 & R & Always return zero.\\\hline
|
|
8--12 & R/W & Two digit BCD month\\\hline
|
|
6--7 & R & Always return zero.\\\hline
|
|
0--5 & R/W & Two digit BCD day of month\\\hline
|
|
\end{bitlist}
|
|
\caption{Date Register Bit Definitions}\label{tbl:datebits}
|
|
\end{center}\end{table}
|
|
Further, according to the common calendar convention, the minimum day and month
|
|
are one and not zero.
|
|
|
\chapter{Wishbone Datasheet}\label{chap:wishbone}
|
\chapter{Wishbone Datasheet}\label{chap:wishbone}
|
Tbl.~\ref{tbl:wishbone}
|
Tbl.~\ref{tbl:wishbone}
|
\begin{table}[htbp]
|
\begin{table}[htbp]
|
\begin{center}
|
\begin{center}
|
\begin{wishboneds}
|
\begin{wishboneds}
|
| Line 439... |
Line 480... |
\end{tabular}\\\hline
|
\end{tabular}\\\hline
|
\end{wishboneds}
|
\end{wishboneds}
|
\caption{Wishbone Datasheet}\label{tbl:wishbone}
|
\caption{Wishbone Datasheet}\label{tbl:wishbone}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
is required by the wishbone specification, and so
|
is required by the wishbone specification, and so
|
it is included here. The big thing to notice is that this real time clock
|
it is included here. The big thing to notice is that both the real time clock
|
acts as a wishbone slave, and that all accesses to the
|
and the real time date modules act as wishbone slaves, and that all accesses
|
clock registers are 32--bit reads and writes. The address bus does not offer
|
to the registers of either module are 32--bit reads and writes. The address
|
|
bus does not offer
|
byte level, but rather 32--bit word level resolution. Select lines are not
|
byte level, but rather 32--bit word level resolution. Select lines are not
|
implemented. Bit ordering is the normal ordering where bit~31 is the most
|
implemented. Bit ordering is the normal ordering where bit~31 is the most
|
significant bit and so forth. Although the stall line is implemented, it is
|
significant bit and so forth. Although the stall line is implemented, it is
|
always zero. Access delays are a single clock, so the clock after a read or
|
always zero. Access delays are a single clock, so the clock after a read or
|
write is placed on the bus the {\tt i\_wb\_ack} line will be high.
|
write is placed on the bus the {\tt i\_wb\_ack} line will be high.
|
| Line 468... |
Line 510... |
\end{center}\end{table}
|
\end{center}\end{table}
|
|
|
\fi
|
\fi
|
|
|
\chapter{I/O Ports}\label{chap:ioports}
|
\chapter{I/O Ports}\label{chap:ioports}
|
The I/O ports for this core are shown in Tbls.~\ref{tbl:iowishbone}
|
The I/O ports for this clock are shown in Tbls.~\ref{tbl:iowishbone}
|
\begin{table}[htbp]
|
\begin{table}[htbp]
|
\begin{center}
|
\begin{center}
|
\begin{portlist}
|
\begin{portlist}
|
|
i\_clk & 1 & Input & System clock, used for time and wishbone interfaces.\\\hline
|
i\_wb\_cyc & 1 & Input & Wishbone bus cycle wire.\\\hline
|
i\_wb\_cyc & 1 & Input & Wishbone bus cycle wire.\\\hline
|
i\_wb\_stb & 1 & Input & Wishbone strobe.\\\hline
|
i\_wb\_stb & 1 & Input & Wishbone strobe.\\\hline
|
i\_wb\_we & 1 & Input & Wishbone write enable.\\\hline
|
i\_wb\_we & 1 & Input & Wishbone write enable.\\\hline
|
i\_wb\_addr & 5 & Input & Wishbone address.\\\hline
|
i\_wb\_addr & 5 & Input & Wishbone address.\\\hline
|
i\_wb\_data & 32 & Input & Wishbone bus data register for use when writing
|
i\_wb\_data & 32 & Input & Wishbone bus data register for use when writing
|
| Line 504... |
Line 547... |
will take place when only the hours and minutes can be
|
will take place when only the hours and minutes can be
|
displayed.\\\hline
|
displayed.\\\hline
|
o\_interrupt & 1 & Output & A pulsed/strobed interrupt line. When the
|
o\_interrupt & 1 & Output & A pulsed/strobed interrupt line. When the
|
clock needs to generate an interrupt, it will set this line
|
clock needs to generate an interrupt, it will set this line
|
high for one clock cycle. \\\hline
|
high for one clock cycle. \\\hline
|
|
o\_ppd & 1 & Output & A `pulse per day' signal which can be fed into the
|
|
real--time date module. This line will be high on the clock before
|
|
the stroke of midnight, allowing the date module to turn over to the
|
|
next day at exactly the same time the clock module turns over to the
|
|
next day.\\\hline
|
i\_hack & 1 & Input & When this line is raised, copies are made of the
|
i\_hack & 1 & Input & When this line is raised, copies are made of the
|
internal state registers on the next clock. These registers can then
|
internal state registers on the next clock. These registers can then
|
be used for an accurate time hack regarding the state of the clock
|
be used for an accurate time hack regarding the state of the clock
|
at the time this line was strobed.\\\hline
|
at the time this line was strobed.\\\hline
|
\end{portlist}
|
\end{portlist}
|
| Line 547... |
Line 595... |
out. The line will not remain high, but neither will it trigger a second
|
out. The line will not remain high, but neither will it trigger a second
|
time until the underlying interrupt is cleared. That is, the timer will only
|
time until the underlying interrupt is cleared. That is, the timer will only
|
trigger once until cleared as will the alarm, but the alarm may trigger after
|
trigger once until cleared as will the alarm, but the alarm may trigger after
|
the timer has triggered and before the timer clears.
|
the timer has triggered and before the timer clears.
|
|
|
|
As a fourth additional line, the clock module produces a one pulse per day
|
|
signal, {\tt o\_ppd}. This signal is designed to be the only necessary
|
|
coordinated input between the clock and date module. Feeding it straight
|
|
into the date module will keep the two synchronized.
|
|
|
The final other I/O line is a simple input line. This line is expected to be
|
The final other I/O line is a simple input line. This line is expected to be
|
strobed for one clock cycle any time a time hack is required. For example,
|
strobed for one clock cycle any time a time hack is required. For example,
|
should you wish to read and synchronize to a GPS PPS signal, strobe the device
|
should you wish to read and synchronize to a GPS PPS signal, strobe the device
|
with the PPS (after dealing with any metastability issues), and read the time
|
with the PPS (after dealing with any metastability issues), and read the time
|
hacks that are produced.
|
hacks that are produced.
|
|
|
|
The real--time date module has a similar set of I/O ports to the clock. These
|
|
are listed in Tbl.~\ref{tbl:iodate}.
|
|
\begin{table}[htbp]
|
|
\begin{center}
|
|
\begin{portlist}
|
|
i\_clk & 1 & Input & The system clock.\\\hline
|
|
i\_ppd & 1 & Input & The one pulse per day strobe from the clock module.\\\hline
|
|
i\_wb\_cyc & 1 & Input & Wishbone bus cycle.\\\hline
|
|
i\_wb\_stb & 1 & Input & Wishbone strobe.\\\hline
|
|
i\_wb\_we & 1 & Input & Wishbone write enable.\\\hline
|
|
i\_wb\_data & 32 & Input & Wishbone bus data register for use when writing
|
|
(configuring) the core from the bus.\\\hline
|
|
o\_wb\_ack & 1 & Output & Equal to the bus cycle line anded with the strobe
|
|
line, and delayed by one clock---essentially acknowledging any
|
|
wishbone access.\\\hline
|
|
o\_wb\_stall & 1 & Output & Fixed to zer.\\\hline
|
|
o\_wb\_data & 32 & Output & Wishbone data bus, returning data values read
|
|
from the interface.\\\hline
|
|
\end{portlist}
|
|
\caption{Wishbone I/O Ports}\label{tbl:iodate}
|
|
\end{center}\end{table}
|
|
There are two big things to notice. The first is the {\tt i\_ppd} signal.
|
|
This should be connected straight from the clock module's {\tt o\_ppd} signal
|
|
into this module. The second difference is the lack of any address lines.
|
|
This is appropriate since the date module provides a single register only.
|
|
|
% Appendices
|
% Appendices
|
% Index
|
% Index
|
\end{document}
|
\end{document}
|
|
|
|
|
