URL
https://opencores.org/ocsvn/rtcclock/rtcclock/trunk
[/] [rtcclock/] [trunk/] [rtl/] [rtcclock.v] - Diff between revs 2 and 3
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 2 |
Rev 3 |
| Line 57... |
Line 57... |
output wire [15:0] o_led;
|
output wire [15:0] o_led;
|
output wire o_interrupt;
|
output wire o_interrupt;
|
input i_hack;
|
input i_hack;
|
|
|
reg [31:0] clock, stopwatch, ckspeed;
|
reg [31:0] clock, stopwatch, ckspeed;
|
reg [17:0] timer;
|
reg [25:0] timer;
|
|
|
wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
|
wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
|
assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
|
assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
|
assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
|
assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
|
assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
|
assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
