| Line 43... |
Line 43... |
// i_btn,
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// i_btn,
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// Output registers
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// Output registers
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o_data, // multiplexed based upon i_wb_addr
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o_data, // multiplexed based upon i_wb_addr
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// Output controls
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// Output controls
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o_sseg, o_led, o_interrupt,
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o_sseg, o_led, o_interrupt,
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//
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o_ppd,
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// Time setting hack(s)
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// Time setting hack(s)
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i_hack);
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i_hack);
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input i_clk;
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input i_clk;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [2:0] i_wb_addr;
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input [2:0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// input i_btn;
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// input i_btn;
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output reg [31:0] o_data;
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output reg [31:0] o_data;
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output reg [31:0] o_sseg;
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output reg [31:0] o_sseg;
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output wire [15:0] o_led;
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output wire [15:0] o_led;
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output wire o_interrupt;
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output wire o_interrupt, o_ppd;
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input i_hack;
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input i_hack;
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reg [31:0] clock, stopwatch, ckspeed;
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reg [31:0] clock, stopwatch, ckspeed;
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reg [25:0] timer;
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reg [25:0] timer;
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| Line 122... |
Line 124... |
clock[21:20] <= clock[21:20] + 2'h1;
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clock[21:20] <= clock[21:20] + 2'h1;
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end else begin
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end else begin
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clock[19:16] <= clock[19:16] + 4'h1;
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clock[19:16] <= clock[19:16] + 4'h1;
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end
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end
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end
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end
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// ppd <= (clock{15:8] == 8'h59);
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ck_ppd <= (clock[21:0] == 22'h235959);
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if ((ck_sel)&&(i_wb_we))
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if ((ck_sel)&&(i_wb_we))
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begin
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begin
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if (8'hff != i_wb_data[7:0])
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if (8'hff != i_wb_data[7:0])
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begin
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begin
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| Line 478... |
Line 481... |
ledreg[10], ledreg[11], ledreg[12], ledreg[13],
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ledreg[10], ledreg[11], ledreg[12], ledreg[13],
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ledreg[14], ledreg[15], ledreg[16], ledreg[17] };
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ledreg[14], ledreg[15], ledreg[16], ledreg[17] };
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assign o_interrupt = tm_int || al_int;
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assign o_interrupt = tm_int || al_int;
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// A once-per day strobe, on the last second of the day so that the
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// the next clock is the first clock of the day. This is useful for
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// connecting this module to a year/month/date date/calendar module.
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assign o_ppd = (ck_ppd)&&(ck_pps);
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always @(posedge i_clk)
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always @(posedge i_clk)
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case(i_wb_addr[2:0])
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case(i_wb_addr[2:0])
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3'b000: o_data <= { clock[31:22], ck_last_clock };
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3'b000: o_data <= { clock[31:22], ck_last_clock };
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3'b001: o_data <= { 6'h00, timer };
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3'b001: o_data <= { 6'h00, timer };
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3'b010: o_data <= stopwatch;
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3'b010: o_data <= stopwatch;
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