| Line 43... |
Line 43... |
// i_btn,
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// i_btn,
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// Output registers
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// Output registers
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o_data, // multiplexed based upon i_wb_addr
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o_data, // multiplexed based upon i_wb_addr
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// Output controls
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// Output controls
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o_sseg, o_led, o_interrupt,
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o_sseg, o_led, o_interrupt,
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//
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// A once-per-day strobe on the last clock of the day
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o_ppd,
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o_ppd,
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// Time setting hack(s)
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// Time setting hack(s)
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i_hack);
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i_hack);
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input i_clk;
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input i_clk;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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| Line 421... |
Line 421... |
hack_time <= { clock[21:0], ck_sub };
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hack_time <= { clock[21:0], ck_sub };
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r_hack_carry <= 1'b0;
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r_hack_carry <= 1'b0;
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end
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end
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|
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reg [15:0] h_sseg;
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reg [15:0] h_sseg;
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reg [3:0] dmask;
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reg [3:1] dmask;
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always @(posedge i_clk)
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always @(posedge i_clk)
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case(clock[27:24])
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case(clock[27:24])
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4'h1: begin h_sseg <= timer[15:0];
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4'h1: begin h_sseg <= timer[15:0];
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if (tm_alarm) dmask <= 4'hf;
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if (tm_alarm) dmask <= 3'h7;
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else begin
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else begin
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dmask[3] <= (12'h000 != timer[23:12]); // timer[15:12]
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dmask[3] <= (12'h000 != timer[23:12]); // timer[15:12]
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dmask[2] <= (16'h000 != timer[23: 8]); // timer[11: 8]
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dmask[2] <= (16'h000 != timer[23: 8]); // timer[11: 8]
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dmask[1] <= (20'h000 != timer[23: 4]); // timer[ 7: 4]
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dmask[1] <= (20'h000 != timer[23: 4]); // timer[ 7: 4]
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dmask[0] <= 1'b1; // Always on
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// dmask[0] <= 1'b1; // Always on
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end end
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end end
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4'h2: begin h_sseg <= stopwatch[19:4];
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4'h2: begin h_sseg <= stopwatch[19:4];
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dmask[3] <= (12'h00 != stopwatch[27:16]);
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dmask[3] <= (12'h00 != stopwatch[27:16]);
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dmask[2] <= (16'h000 != stopwatch[27:12]);
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dmask[2] <= (16'h000 != stopwatch[27:12]);
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dmask[1] <= 1'b1; // Always on, stopwatch[11:8]
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dmask[1] <= 1'b1; // Always on, stopwatch[11:8]
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dmask[0] <= 1'b1; // Always on, stopwatch[7:4]
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// dmask[0] <= 1'b1; // Always on, stopwatch[7:4]
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end
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end
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4'h3: begin h_sseg <= ck_last_clock[15:0];
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4'h3: begin h_sseg <= ck_last_clock[15:0];
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dmask[3:0] <= 4'hf;
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dmask[3:1] <= 3'h7;
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end
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end
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default: begin // 4'h0
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default: begin // 4'h0
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h_sseg <= { 2'b00, ck_last_clock[21:8] };
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h_sseg <= { 2'b00, ck_last_clock[21:8] };
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dmask[2:0] <= 3'hf;
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dmask[2:1] <= 2'b11;
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dmask[3] <= (2'b00 != ck_last_clock[21:20]);
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dmask[3] <= (2'b00 != ck_last_clock[21:20]);
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end
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end
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endcase
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endcase
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|
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wire [31:0] w_sseg;
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wire [31:0] w_sseg;
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| Line 466... |
Line 466... |
else
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else
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o_sseg <= {
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o_sseg <= {
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(dmask[3])?w_sseg[31:24]:8'h00,
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(dmask[3])?w_sseg[31:24]:8'h00,
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(dmask[2])?w_sseg[23:16]:8'h00,
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(dmask[2])?w_sseg[23:16]:8'h00,
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(dmask[1])?w_sseg[15: 8]:8'h00,
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(dmask[1])?w_sseg[15: 8]:8'h00,
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(dmask[0])?w_sseg[ 7: 0]:8'h00 };
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w_sseg[ 7: 0] };
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|
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reg [17:0] ledreg;
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reg [17:0] ledreg;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((ck_pps)&&(ck_ppm))
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if ((ck_pps)&&(ck_ppm))
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ledreg <= 18'h00;
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ledreg <= 18'h00;
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